ksz8851-mql Micrel Semiconductor, ksz8851-mql Datasheet - Page 67

• Manufacturer Part Number: ksz8851-mql
• Description: Single-port Ethernet Mac Controller With 8/16-bit Or 32-bit Non-pci Interface
• Manufacturer: Micrel Semiconductor

MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2
Multicast table register 2.
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3
Multicast table register 3.
0xA8 – 0xAF: Reserved
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR
This register is used to control the flow control for low watermark in QMU RX queue.
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR
This register is used to control the flow control for high watermark in QMU RX queue.
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR
This register is used to control the flow control for overrun watermark in QMU RX queue
February 2009
Micrel, Inc.
Bit
15-0
Bit
15-0
Bit
15-0
Bit
15-12
11-0
Bit
15-12
11-0
Bit
15-12
11-0
-
-
-
Default Value
0x0
Default Value
0x0
Default Value
0x0
Default Value
0x0500
Default Value
0x0300
Default Value
0x0040
R/W
RW
R/W
RW
R/W
RW
R/W
RW
RW
R/W
RW
RW
R/W
RW
RW
Description
HT1 Hash Table 1
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1,
all multicast addresses are received regardless of the multicast table value.
Description
HT2 Hash Table 2
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1,
all multicast addresses are received regardless of the multicast table value.
Description
HT3 Hash Table 3
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1,
all multicast addresses are received regardless of the multicast table value.
Description
Reserved
FCLWC Flow Control Low Watermark Configuration
These bits are used to define the QMU RX queue low watermark configuration. It is in
double words count and default is 5.12 KByte available buffer space out of 12 KByte.
Description
Reserved
FCHWC Flow Control High Watermark Configuration
These bits are used to define the QMU RX queue high watermark configuration. It is in
double words count and default is 3.072 KByte available buffer space out of 12 KByte.
Description
Reserved
FCLWC Flow Control Overrun Watermark Configuration
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KSZ8851-16/32 MQL/MQLI
M9999-021309-1.1