ksz8851-mql Micrel Semiconductor, ksz8851-mql Datasheet - Page 71

• Manufacturer Part Number: ksz8851-mql
• Description: Single-port Ethernet Mac Controller With 8/16-bit Or 32-bit Non-pci Interface
• Manufacturer: Micrel Semiconductor

0xDA – 0xDF: Reserved
0xE0 – 0xE3: Reserved
PHY 1 MII-Register Basic Control Register (0xE4 – 0xE5): P1MBCR
This register contains Media Independent Interface (MII) register for port 1 as defined in the IEEE 802.3 specification.
February 2009
Micrel, Inc.
15-1
0
Bit
15
14
13
12
11-10
9
8
7-6
5
4
3
2
1
0
Default
0
0
1
1
0
0
1
0
1
0
0
0
0
0
-
0
RW
WO
(Self clear)
R/W
RO
RW
RW
RW
RW
RW
RW
RO
R/W
RW
RW
RW
RW
RW
Reserved.
PHY Reset Bit
This bit is write only and self clear after write an “1”, it is used to reset PHY block circuitry.
Description
Reserved
Local (far-end) loopback (llb)
1 = perform local loopback at host
(host Tx -> PHY -> host Rx, see Figure 11)
0 = normal operation
Force 100
1 = force 100Mbps if AN is disabled (bit 12)
0 = force 10Mbps if AN is disabled (bit 12)
AN Enable
1 = auto-negotiation enabled.
0 = auto-negotiation disabled.
Reserved
Restart AN
1 = restart auto-negotiation.
0 = normal operation.
Force Full Duplex
1 = force full duplex
0 = force half duplex.
if AN is disabled (bit 12) or AN is enabled but failed.
Reserved
HP_mdix
1 = HP Auto MDI-X mode.
0 = Micrel Auto MDI-X mode.
Force MDI-X
1 = force MDI-X.
0 = normal operation.
Disable MDI-X
1 = disable auto MDI-X.
0 = normal operation.
Reserved.
Disable Transmit
1 = disable transmit.
0 = normal operation.
Disable LED
1 = disable all LEDs.
0 = normal operation.
71
Bit is same as:
Bit 6 in P1CR
Bit 7 in P1CR
Bit 13 in P1CR
Bit 5 in P1CR
Bit 15 in P1SR
Bit 9 in P1CR
Bit 10 in P1CR
Bit 14 in P1CR
Bit 15 in P1CR
KSZ8851-16/32 MQL/MQLI
M9999-021309-1.1