mc68hc908gr8a Freescale Semiconductor, Inc, mc68hc908gr8a Datasheet - Page 70

• Manufacturer Part Number: mc68hc908gr8a
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
4.5.6 PLL Reference Divider Select Register
The PLL reference divider select register (PMDS) contains the programming information for the modulo
reference divider.
RDS3–RDS0 — Reference Divider Select Bits
4.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as logic 0.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry
into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can
be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock
frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency
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register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See
Clock Selector Circuit
$40 for a default range multiply value of 64.
These read/write bits control the modulo reference divider that selects the reference division factor, R.
(See
PLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the
reference divider the same as a value of $01. (See
initializes the register to $01 for a default divide value of 1.
4.3.3 PLL Circuits
Address: $003B
The VCO range select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
The default divide value of 1 is recommended for all applications.
Reset:
Read:
Write:
Figure 4-9. PLL Reference Divider Select Register (PMDS)
Bit 7
0
0
and
and
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
4.3.7 Special Programming
= Unimplemented
4.3.6 Programming the
6
0
0
5
0
0
NOTE
NOTE
4
0
0
4.3.7 Special Programming
PLL.) RDS7–RDS0 cannot be written when the
Exceptions.). Reset initializes the register to
RDS3
3
0
RDS2
2
0
RDS1
1
0
Exceptions.) Reset
Freescale Semiconductor
RDS0
Bit 0
1
4.3.8 Base