mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 220

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI)
20.12.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
20.12.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
See
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. See
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. See
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. See
220
20.5 Transmission
Note 1. X = Don’t care
SPE
0
1
1
1
A high voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
SPMSTR
MASTER SS
MISO/MOSI
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
X
0
1
1
(1)
Formats. Since it is used to indicate the start of a transmission, the SS must be
MODFEN
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
X
X
0
1
Table
Figure 20-12. CPHA/SS Timing
BYTE 1
Table 20-3. SPI Configuration
Master without MODF
SPI Configuration
Master with MODF
20-3.
Not enabled
Slave
NOTE
Figure
BYTE 2
20-12.
General-purpose I/O; SS ignored by SPI
General-purpose I/O; SS ignored by SPI
20.7.2 Mode Fault
20.13.2 SPI Status and Control
State of SS Logic
Input-only to SPI
Input-only to SPI
BYTE 3
Error. For the state of
Freescale Semiconductor
Register.