mc68hc05p18a Freescale Semiconductor, Inc, mc68hc05p18a Datasheet - Page 96

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mc68hc05p18a

Manufacturer Part Number
mc68hc05p18a
Description
Mc68hc05p18a Hcmos Microcontroller Unit
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Analog-to-Digital (A/D) Converter
11.7 A/D Conversion Value Data Register
11.8 A/D Subsystem Operation during Wait Mode and Halt Mode
11.9 A/D Subsystem Operation during Stop Mode
Technical Data
Address:
This register contains the output of the A/D converter. See
The A/D subsystem continues normal operation during wait mode and
halt mode. To decrease power consumption during wait or halt, the
ADON bit in the ADSC register and the EERC bit in the EEPROG
register should be cleared if the A/D subsystem is not being used.
When stop mode is enabled, execution of the STOP instruction
terminates all A/D subsystem functions. Any pending conversion is
aborted. When the oscillator resumes operation upon leaving the stop
mode, a finite amount of time passes before the A/D subsystem
stabilizes sufficiently to provide conversions at its rated accuracy. The
delays built into the MC68HC05P18A when coming out of stop mode are
sufficient for this purpose. No explicit delays need to be added to the
application software.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
Figure 11-2. A/D Conversion Value Data Register (ADC)
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Bit 7
AD7
Analog-to-Digital (A/D) Converter
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= Unimplemented
AD6
6
AD5
5
Unaffected by reset
AD4
R
4
= Reserved
AD3
3
AD2
2
MC68HC05P18A
Figure
AD1
1
11-2.
Bit 0
AD0

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