mc68hc05bd3 Freescale Semiconductor, Inc, mc68hc05bd3 Datasheet
mc68hc05bd3
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mc68hc05bd3 Summary of contents
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... HC05 MC68HC05BD3 MC68HC705BD3 MC68HC05BD5 TECHNICAL DATA MC68HC05BD3D/H ...
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GENERAL DESCRIPTION PIN DESCRIPTION AND I/O PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS MULTI-FUNCTION TIMER PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BD3 MC68HC05BD5 ...
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GENERAL DESCRIPTION 2 PIN DESCRIPTION AND I/O PORTS 3 MEMORY AND REGISTERS 4 RESETS AND INTERRUPTS 5 MULTI-FUNCTION TIMER 6 PULSE WIDTH MODULATION 7 M-BUS SERIAL INTERFACE 8 SYNC SIGNAL PROCESSOR 9 CPU CORE AND INSTRUCTION SET 10 LOW ...
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... MC68HC05BD3 MC68HC705BD3 MC68HC05BD5 High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit TPG ...
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Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; ...
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... CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05BD3D/H) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category. ...
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... Motorola Semiconductors H.K. Ltd., 13/F, Prosperity Centre, 77-81 Container Port Road, Kwai Chung, N.T., HONG KONG. F.A.O. HKG CSIC Technical Publications (re: MC68HC05BD3D/H) FAX: (852) 2485-0548 – Third fold back along this line – Phone No: FAX No: – Finally, tuck this edge into opposite flap – FIX STAMP HERE ...
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... PIN DESCRIPTIONS.............................................................................................2-1 2.2 Pin Assignments ....................................................................................................2-2 2.3 INPUT/OUTPUT PORTS.......................................................................................2-3 2.3.1 Port A ...............................................................................................................2-3 2.3.2 Port B ...............................................................................................................2-3 2.3.3 Port C ...............................................................................................................2-4 2.3.4 Port D ...............................................................................................................2-4 2.3.5 Input/Output Programming...............................................................................2-4 2.3.6 Port C and D Configuration Registers..............................................................2-5 3.1 Registers ...............................................................................................................3-1 3.2 RAM (MC68HC05BD3)..........................................................................................3-1 3.3 RAM (MC68HC705BD3/MC68HC05BD5).............................................................3-1 3.4 ROM (MC68HC05BD3) .........................................................................................3-2 3.5 ROM (MC68HC05BD5) .........................................................................................3-2 3.6 EPROM (MC68HC705BD3) ..................................................................................3-2 3.7 Bootstrap ROM ......................................................................................................3-2 MC68HC05BD3 TITLE 1 GENERAL DESCRIPTION 2 3 MEMORY AND REGISTERS Page Number TPG i ...
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... General Operation .................................................................................................6-1 7.1 M-Bus Interface Features ......................................................................................7-1 7.2 M-Bus Protocol ......................................................................................................7-2 7.2.1 START Signal...................................................................................................7-3 7.2.2 Slave Address Transmission ............................................................................7-3 7.2.3 Data Transfer....................................................................................................7-4 7.2.4 Repeated START Signal ..................................................................................7-4 7.2.5 STOP Signal ....................................................................................................7-4 7.2.6 Arbitration Procedure.......................................................................................7-4 7.2.7 Clock Synchronization .....................................................................................7-5 7.2.8 Handshaking....................................................................................................7-5 7.3 M-Bus Registers ....................................................................................................7-5 ii TITLE 4 RESETS AND INTERRUPTS 5 MULTI-FUNCTION TIMER 6 PULSE WIDTH MODULATION 7 M-BUS SERIAL INTERFACE Page Number TPG MC68HC05BD3 ...
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... Line Frequency Registers (LFRs) ....................................................................8-9 8.3.4 Sync Signal Control Register (SSCR)..............................................................8-10 8.3.5 Horizontal Sync Period Width Register (HPWR)..............................................8-10 8.4 System Operation ..................................................................................................8-11 CPU CORE AND INSTRUCTION SET 9.1 Registers ...............................................................................................................9-1 9.1.1 Accumulator (A) ...............................................................................................9-1 9.1.2 Index register (X)..............................................................................................9-2 9.1.3 Program counter (PC) ......................................................................................9-2 9.1.4 Stack pointer (SP) ............................................................................................9-2 9.1.5 Condition code register (CCR).........................................................................9-2 MC68HC05BD3 TITLE 8 SYNC SIGNAL PROCESSOR 9 Page Number TPG iii ...
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... STOP Mode.........................................................................................................10-1 10.2 WAIT Mode..........................................................................................................10-1 10.3 COP Watchdog Timer Considerations.................................................................10-2 11.1 User Mode (Normal Operation) ...........................................................................11-2 11.2 Self-Check Mode .................................................................................................11-2 11.3 Bootstrap Mode ...................................................................................................11-4 12.1 Maximum Ratings................................................................................................12-1 12.2 Thermal Characteristics ......................................................................................12-1 12.3 DC Electrical Characteristics...............................................................................12-2 12.4 Control Timing .....................................................................................................12-3 12.5 M-Bus Timing ......................................................................................................12-4 12.6 Sync Signal Processor Timing.............................................................................12-5 iv TITLE 10 LOW POWER MODES 11 OPERATING MODES 12 ELECTRICAL SPECIFICATIONS Page Number TPG MC68HC05BD3 ...
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... Paragraph Number MECHANICAL SPECIFICATIONS 13.1 42-Pin SDIP Package (Case 858-01) ..................................................................13-1 13.2 40-Pin DIP Package (Case 711-03).....................................................................13-1 14.1 Features...............................................................................................................14-1 14.2 Memory Map........................................................................................................14-1 14.3 EPROM Programming .........................................................................................14-1 14.3.1 Programming Control Register (PCR)............................................................14-3 14.3.2 EPROM Programming Sequence ..................................................................14-3 14.4 DC Electrical Characteristics ...............................................................................14-4 15.1 Features...............................................................................................................15-1 15.2 Memory Map........................................................................................................15-1 15.3 DC Electrical Characteristics ...............................................................................15-3 MC68HC05BD3 TITLE 13 14 MC68HC705BD3 15 MC68HC05BD5 Page Number TPG v ...
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... LIST OF FIGURES Figure Number 1-1 MC68HC05BD3/MC68HC705BD3/MC68HC05BD5 Block Diagram ......................1-2 2-1 Pin Assignment for 40-pin DIP Package.................................................................2-2 2-2 Pin Assignment for 42-pin SDIP Package ..............................................................2-3 2-3 Parallel Port I/O Circuitry ........................................................................................2-6 3-1 Memory Map ..........................................................................................................3-3 4-1 Power-On Reset and RESET Timing......................................................................4-2 4-2 Interrupt Stacking Order .........................................................................................4-4 4-3 External Interrupt Circuit and Timing ......................................................................4-6 6-1 8-Bit PWM Output Waveforms................................................................................6-2 7-1 M-Bus Interface Block Diagram ...
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... THIS PAGE LEFT BLANK INTENTIONALLY viii TPG MC68HC05BD3 ...
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... Read/modify/write instructions ...............................................................................9-7 9-6 Control instructions.................................................................................................9-7 9-7 Instruction set .........................................................................................................9-8 9-8 M68HC05 opcode map...........................................................................................9-10 11-1 Mode Selection.....................................................................................................11-2 11-2 Self-Check Report ................................................................................................11-4 12-1 DC Electrical Characteristics for MC68HC05BD3 ................................................12-2 12-2 Control Timing ......................................................................................................12-3 12-3 M-Bus Interface Input Signal Timing.....................................................................12-4 12-4 M-Bus Interface Output Signal Timing..................................................................12-4 12-5 Sync Signal Processor Timing..............................................................................12-5 14-1 MC68HC705BD3 Programming Boards...............................................................14-1 14-2 DC Electrical Characteristics for MC68HC705BD3 ..............................................14-4 15-1 DC Electrical Characteristics for MC68HC05BD5 ...
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... THIS PAGE LEFT BLANK INTENTIONALLY x TPG MC68HC05BD3 ...
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... GENERAL DESCRIPTION The MC68HC05BD3 HCMOS microcontroller is a member of the M68HC05 Family of low-cost single-chip microcontrollers. This 8-bit microcontroller unit (MCU) contains an on-chip oscillator, CPU, RAM, ROM, parallel I/O capability with pins programmable as input or output, M-Bus serial 2 interface system (I C), Pulse Width Modulator, Multi-Function Timer, and Sync Signal Processor. ...
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... BOOTSTRAP ROM - 480 Bytes for MC68HC705BD3 only M68HC05 CPU IRQ/ VPP RESET RESET MFT (with COP) EXTAL OSC 2 XTAL VDD VSS Figure 1-1 MC68HC05BD3/MC68HC705BD3/MC68HC05BD5 Block Diagram 1-2 USER ROM 7 0 ACCUMULATOR 7 0 INDEX REGISTER STACK POINTER 4 0 PROGRAM COUNTER ...
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... PIN DESCRIPTION AND I/O PORTS This section provides a description of the functional pins and I/O programming of the MC68HC05BD3 microcontroller. 2.1 PIN DESCRIPTIONS 40-pin DIP PIN NAME PIN No. VDD, VSS 5, 6 IRQ/ VPP 15 RESET 4 XTAL, EXTAL 7, 8 PA0-PA7 23-16 PB0-PB5 14-9 PC0/PWM8 to 26-31 PC5/PWM13 MC68HC05BD3 PIN DESCRIPTION AND I/O PORTS ...
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... PB4 10 31 PC5/PWM13 PB3 11 30 PC4/PWM12 PB2 12 29 PC3/PWM11 PB1 13 28 PC2/PWM10 PB0 14 27 PC1/PWM9 IRQ/ VPP 15 26 PC0/PWM8 PA7 16 25 PD1/SCL PA6 17 24 PD0/SDA PA5 18 23 PA0 PA4 19 22 PA1 PA3 20 21 PA2 PIN DESCRIPTION AND I/O PORTS DESCRIPTION TPG MC68HC05BD3 ...
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... PB5 are +10V open-drain port pins. The Port B data register is at $01 and the data direction register (DDR $05. Reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. MC68HC05BD3 PIN DESCRIPTION AND I/O PORTS PWM2 1 ...
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... The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin output mode. The output data latch is read. PIN DESCRIPTION AND I/O PORTS TPG MC68HC05BD3 ...
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... PWM15 and PWM14 in $000A. That is, HTTL and VTTL settings override PWM15 and PWM14 settings. Table 2-2 Configuration for PC6 and PC7 PWM15 HTTL MC68HC05BD3 PIN DESCRIPTION AND I/O PORTS bit 6 bit 5 bit 4 bit 3 bit 6 bit 5 bit 4 bit 3 HTTL VTTL Result of PC7 ...
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... DDR 6 DDR 5 DDR 4 Px7 Px6 Px5 Px4 (b) V & (c) Figure 2-3 Parallel Port I/O Circuitry PIN DESCRIPTION AND I/O PORTS OUTPUT I/O PIN DDR 3 DDR 2 DDR 1 DDR 0 Px3 Px2 Px1 Px0 DD NOTE: ( INPUT PROTECTION (2) LATCH-UP PROTECTION NOT SHOWN PAD IP MC68HC05BD3 TPG ...
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... ROM/ EPROM , user RAM, self-check/ bootstrap ROM, and I/O as shown in Figure 3-1. 3.1 Registers All the I/O, control and status registers of the MC68HC05BD3 are contained within the first 48-byte block of the memory map (address $0000 to $002F). 3.2 RAM (MC68HC05BD3) The user RAM consists of 128 bytes of memory, from $0080 to $00FF. This is shared with a 64 byte stack area ...
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... ROM (MC68HC05BD3) The user ROM consists of 3.75K-bytes of memory, from $3000 to $3EFF. 3 3.5 ROM (MC68HC05BD5) The user ROM consists of 7.75K-bytes of memory, from $2000 to $3EFF. 3.6 EPROM (MC68HC705BD3) The user EPROM consists of 7.75K-bytes of memory, from $2000 to $3EFF. 3.7 Bootstrap ROM This is available on the MC68HC705BD3 device only. It stores the on-chip program for programming the user EPROM ...
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... Bytes 224 Bytes $3FDF $3FDF $3FE0 $3FE0 Self-Check Self-Check Vectors 16 Bytes $3FEF $3FEF $3FF0 $3FF0 User Vectors User Vectors 16 Bytes $3FFF $3FFF MC68HC05BD3 MC68HC705BD3 $0000 I/O I/O 48 Bytes 48 Bytes $002F $0030 Unused Unused $007F $0080 $00C0 Stack 64 Bytes $00FF User RAM 256 Bytes ...
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... LF11 LF10 LF9 LF8 0000 0000 LF3 LF2 LF1 LF0 0000 0000 0000 0000 0000 000- FD3 FD2 FD1 FD0 ---0 0000 TXAK 0000 0--- SRW MIF RXAK 1000 -001 MD3 MD2 MD1 MD0 undefined ELAT PGM ---- --00 MC68HC05BD3 TPG ...
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... MC68HC05BD3 Table 3-1 Register Outline bit 6 bit 5 bit 4 bit 3 10PWM4 10PWM3 10PWM2 10PWM1 10PWM0 10BRM2 10BRM1 10BRM0 11PWM4 11PWM3 11PWM2 11PWM1 11PWM0 11BRM2 11BRM1 11BRM0 12PWM4 12PWM3 12PWM2 12PWM1 12PWM0 12BRM2 12BRM1 12BRM0 ...
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... THIS PAGE LEFT BLANK INTENTIONALLY 3-6 MEMORY AND REGISTERS TPG MC68HC05BD3 ...
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... RESETS The MC68HC05BD3 can be reset in four ways: by the initial power-on reset function active low input to the RESET pin opcode fetch from an illegal address, and by a COP watchdog timer reset. Any of these resets will cause the program its starting address, specified by the contents of memory locations $3FFE and $3FFF, and cause the interrupt mask of the Condition Code register to be set ...
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... The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific amount of time by a program reset sequence. 4-2 4064 t cyc t cyc 3FFE 3FFF NEW PC NEW NEW OP PCL PCH CODE t =1.5t RL CYC 3 Figure 4-1 Power-On Reset and RESET Timing RESETS AND INTERRUPTS 3FFE 3FFE 3FFF NEW PC OP PCL PCH CODE MC68HC05BD3 TPG ...
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... I-bit in the CCR. If the I-bit is zero (interrupt enabled), SWI is executed after interrupts that were pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The SWI interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD. MC68HC05BD3 RESETS AND INTERRUPTS 4 TPG ...
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... OF STACK) Vector Address Priority RESET $3FFE-$3FFF highest SWI $3FFC-$3FFD IRQ $3FFA-$3FFB SSP $3FF8-$3FF9 MBUS $3FF6-$3FF7 MFT $3FF4-$3FF5 – $3FF2-$3FF3 lowest – $3FF0-$3FF1 MC68HC05BD3 TPG ...
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... Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is recognized. Note: The internal interrupt latch is cleared in the first part of the service routine; therefore, one (and only one) external interrupt pulse could be latched during t as soon as the I bit is cleared. MC68HC05BD3 bit 6 bit 5 bit 4 bit 3 TOF ...
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... CYC interrupt service routine plus 21 tcyc cycles. LEVEL SENSITIVE TRIGGER CONDITION If after servicing an interrupt the IRQ pin remains low, then the next interrupt is recognized. Normally used with wired OR connection. Normally used with pull-up resistors for wired-OR connection. MC68HC05BD3 ILIL TPG ...
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... A byte transfer has been completed. 0 (clear) – A byte is being transfer. MAAS - Addressed as Slave 1 (set) – Currently addressed as a slave. 0 (clear) – Not currently addressed. MC68HC05BD3 bit 6 bit 5 bit 4 bit 3 MCF MAAS MBB MAL RESETS AND INTERRUPTS State bit 2 bit 1 ...
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... A CPU interrupt request will be generated if RTIE is set. RTIF is cleared by writing a “0” to the bit. Refer to Section 5 for detailed description of Multi-Function Timer. 4-8 Address bit 7 bit 6 bit 5 bit 4 $0008 TOF RTIF TOFIE RTIE RESETS AND INTERRUPTS State bit 3 bit 2 bit 1 bit 0 on reset IRQN RT1 RT0 0000 0011 MC68HC05BD3 TPG ...
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... MULTI-FUNCTION TIMER The MFT provides miscellaneous functions to the MC68HC05BD3 MCU. It includes a timer overflow function, real-time interrupt, and COP watchdog. The external interrupt (IRQ) triggering option is also set by this module’s MFT Control and Status Register. The clock base for this module is derived from the bus clock divided by four. For a 2MHz E (CPU) clock, the clock base is 0.5MHz. This clock base is then divided by an 8-stage ripple counter to generate the timer overfl ...
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... Preventing a COP time-out is achieved by writing a “0” to bit 0 of address $3FF0. The COP counter has to be cleared periodically by software with a period less than COP reset rate. The COP watchdog timer is always enabled and continues to count in Wait mode. 5-2 MULTI-FUNCTION TIMER TPG MC68HC05BD3 ...
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... Table 5-1 COP Reset and RTI Rates RT1 RT0 Note: RT0 and RT1 should only be changed immediately after COP watchdog timer has been reset. MC68HC05BD3 Minimum COP reset period COP E clock = 2MHz RTI E/16384/7/1 57.344ms E/16384/1 E/16384/7/2 114.688ms E/16384/2 E/16384/7/4 229.376ms E/16384/4 E/16384/7/8 458 ...
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... THIS PAGE LEFT BLANK INTENTIONALLY 5-4 MULTI-FUNCTION TIMER TPG MC68HC05BD3 ...
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... PULSE WIDTH MODULATION The MC68HC05BD3 has 16 PWM channels. Channel are dedicated PWM channels. Channel are shared with port C I/O pins, and are selected by the respective bits in Configuration register 1. PWM channels are +10V open-drain type; therefore a pull-up resistor is required at each of the pins. ...
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... PWM cycles where pulses are inserted in a 8-cycle frame xx1 x1x 1xx 6-2 32T=16 s 31T 16T 31T Pulse inserted at end of PWM cycle depends on setting Figure 6-1 8-Bit PWM Output Waveforms PULSE WIDTH MODULATION 16T T Number of inserted pulses in a 8-cycle frame TPG MC68HC05BD3 ...
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... Arbitration lost driven interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Generate/detect the start, stop and acknowledge signals • Repeated START signal generation • Bus busy detection MC68HC05BD3 7 M-BUS SERIAL INTERFACE 2 C bus standard. This two-wire TPG 7-1 7 ...
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... SRW M-Bus interrupt M-Bus clock generator sync logic START, STOP generator and arbitration timing sync Figure 7-1 M-Bus Interface Block Diagram M-BUS SERIAL INTERFACE MIF RXAK Frequency Address divider register register Address comparator TX shift RX shift register register TX RX control control MC68HC05BD3 8 TPG ...
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... This is a seven bits long calling address followed by a R/W bit. The R/W bit dictates the slave of the desired direction of data transfer. Only the slave with matched address will respond by sending back an acknowledge bit by pulling the SDA low at the 9th clock; see Figure 7-2. MC68HC05BD3 LSB MSB 1 ...
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... The transition from master to slave mode will not generate a STOP condition. Meanwhile, a software bit will be set by hardware to indicate loss of arbitration. 7-4 M-BUS SERIAL INTERFACE TPG MC68HC05BD3 ...
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... SCL line. 7.3 M-Bus Registers There are five registers used in the M-Bus interface, these are discussed in the following paragraphs. MC68HC05BD3 Start counting high period WAIT Internal counter reset M-BUS SERIAL INTERFACE ...
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... MC68HC05BD3 TPG ...
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... Do not send acknowledge signal. 0 (clear) – Send acknowledge signal at 9th clock bit. If cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data. If set, no acknowledge signal response. This is an active low control bit. MC68HC05BD3 bit 5 bit 4 bit 3 bit 2 ...
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... This arbitration lost flag is set when the M-Bus master loses arbitration during a master transmission mode. When MAL is set, the MIF (M-Bus interrupt) bit is also set. This bit must be cleared by software. 7-8 bit 6 bit 5 bit 4 bit 3 bit 2 MAAS MBB MAL SRW M-BUS SERIAL INTERFACE State bit 1 bit 0 on reset MIF RXAK 1000 0001 TPG MC68HC05BD3 ...
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... In master transmit mode, data written into this register is sent to the bus automatically, with the most significant bit out first. In master receive mode, reading of this register initiates receiving of the next byte data. In slave mode, the same function applies after it has been addressed. MC68HC05BD3 bit 5 bit 4 ...
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... MAAS=1? signal Last 2nd N RX byte to read? TX/RX? Y TXAK=1 ACK from receiver? Read from MDR Write to MDR RTI M-BUS SERIAL INTERFACE N N Arbitration Lost? Y Clear MAL Y N MAAS= SRW= Set RX mode Set TX mode Dummy read MDR Write to MDR MC68HC05BD3 N TPG ...
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... Upon the completion of the transmission or reception of a data byte, the data transferring bit (MCF) will be set, indicating one byte communication has been finished. The M-Bus interrupt bit (MIF) will also be set to generate an M-Bus interrupt if the interrupt is enabled. Software must clear the MC68HC05BD3 ; DISABLE INTERRUPT ; STATUS REGISTER ...
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... IF NO MORE DATA, BRANCH TO ; END ; GET NEXT BYTE OF DATA ; TRANSMIT THE DATA ; DECREASE THE TXCNT ; EXIT ; GENERATE A STOP CONDITION ; RETURN FROM INTERRUPT ; LAST BYTE TO BE READ ; CHECK LAST 2ND BYTE TO BE READ ; NOT LAST ONE OR LAST SECOND M-BUS SERIAL INTERFACE TPG MC68HC05BD3 ...
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... The losing device immediately switches to slave receive mode by M-Bus hardware. Its data output to the SDA line is stopped, but internal transmit clock still runs until the end of the data byte transmission. An interrupt occurs when this dummy byte transmission MC68HC05BD3 ; LAST SECOND, DISABLE ACK ; TRANSMITTING ...
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... STOP condition; an interrupt will be generated and the MAL bit set to indicate that the attempt to acquire the bus has failed. Considering these cases, the slave service routine should test the MAL bit first, and software should clear the MAL bit set. 7 7-14 M-BUS SERIAL INTERFACE TPG MC68HC05BD3 ...
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... Polarity Correction The polarity correction block of the sync signal processor accepts the input sync signals (HSYNC/VSYNC) and converts them to negative polarity signals, regardless of the polarity of the inputs. The following describes the methodologies used in polarity correction. MC68HC05BD3 8 =0.5 s. CYC SYNC SIGNAL PROCESSOR ...
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... FREE CLK GEN. H FREE V H INTERRUPT HSYNC CIRCUIT COUNTER LINE FREQ. $0F INTERRUPT REGISTERS $ the case of positive polarity input CYC ). At power-up or system reset, CYC SYNC SIGNAL PROCESSOR SYNC VDET DETECTOR MUX VTTL R SOUT S R MUX HTTL SYNC HDET DETECTOR TPG MC68HC05BD3 ...
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... The sync detector determines whether the incoming sync signal is active. Both sync high and low pulse widths must be within the specific values to be regarded as active. HDET and VDET flags will be set if the HSYNC and VSYNC signals are active, respectively. MC68HC05BD3 Positive polarity composite sync signal Negative polarity composite sync signal ...
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... FOUT. This CYC load Horizontal sync pulse counter reset count finish Figure 8-3 Sync Separator SYNC SIGNAL PROCESSOR Horizontal Sync Register in out Comparator equal Sync separation logic Sync insertion circuit Hsync Vsync ), a horizontal sync pulse is CYC MC68HC05BD3 TPG ...
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... I-bit in the Condition Code Register (CCR) is cleared. The interrupt will occur at each leading edge of VSYNC. The interrupt vector address is at $3FF8-$3FF9, and the interrupt latch is cleared automatically by fetching of the interrupt vectors. MC68HC05BD3 ), the vertical sync pulse has finished and CYC SYNC SIGNAL PROCESSOR ...
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... Counter resets at 4 PH2 cycles after falling edge of VSYNIN Counter advances at the rising edge of the clock Figure 8-5 Vertical Frequency Counter Timing SYNC SIGNAL PROCESSOR 13-bit Vertical Frequency Register 13-bit counter R R 12-bit counter 12-bit Horizontal Line Count Register MC68HC05BD3 TPG ...
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... Horizontal Sync Signal Detect flag, if set, indicates an active input horizontal sync signal has been detected. If cleared, it indicates there is no active signal, and the HTTL will output the internally generated Hsync signal. An active horizontal sync signal is defined as: HDET=(HSYNC pulse width < 16t MC68HC05BD3 bit 5 bit 4 bit 3 ...
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... When FOUT is cleared, 63.5Hz and 48.8KHz signals are output instead. Reset clears this bits. VSIN - Vsync Input Source This bit selects the source of the input sync signals. Reset clears this bits. 1 (set) – Separated sync signals through VSYNC and HSYNC inputs. 0 (clear) – Composite sync signal through HSYNC input 8-8 SYNC SIGNAL PROCESSOR TPG MC68HC05BD3 ...
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... An internal line counter counts the horizontal sync pulses between two vertical sync pulses. The counted value will be transferred to this register pair. HOVER bit will be set if the incoming horizontal sync pulses between two vertical sync pulses are more than 4096 or there is no vertical MC68HC05BD3 bit 6 bit 5 ...
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... VSYNC. 8-10 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 5 bit 4 bit 3 bit 2 SYNC SIGNAL PROCESSOR State bit 1 bit 0 on reset 0000 0000 State bit 1 bit 0 on reset 0000 0000 is at 2MHz. As the incoming CYC , i.e. 7.8125KHz if t CYC CYC MC68HC05BD3 TPG ...
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... HDET and VDET are both read 1 even VSIN=1. Note: Each time if VDET is not detected when VSIN=1, user needs to clear VSIN to check VDET. If VDET is still not detected, user then set VSIN to check them again to decide what mode it is. MC68HC05BD3 SYNC SIGNAL PROCESSOR 8 TPG 8-11 ...
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... No HSYNC Set Standby mode Clear VSIN=0 Figure 8-6 Typical Monitor System Operation SYNC SIGNAL PROCESSOR Set VSIN=1 Y VDET= HDET= HSYNC signal Set Standby mode Y 1st_time= HDET=1? N Clear VSIN=0 No VSYNC No VSYNC No HSYNC Set Suspend mode Set Off mode A MC68HC05BD3 TPG ...
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... CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05BD3. 9.1 Registers The MCU contains five registers, as shown in the programming model of Figure 9-1. The interrupt stacking order is shown in Figure 9- ...
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... This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. 9-2 7 Condition code register Accumulator Index register Program counter high Program counter low Figure 9-2 Stacking order CPU CORE AND INSTRUCTION SET Stack 0 Decreasing memory address MC68HC05BD3 TPG ...
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... This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 9-1. MC68HC05BD3 CPU CORE AND INSTRUCTION SET 9 TPG ...
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... Tables Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 9-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 9-8). 9-4 CPU CORE AND INSTRUCTION SET TPG MC68HC05BD3 ...
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... BIT A5 (logical compare) Jump unconditional JMP Jump to subroutine JSR MC68HC05BD3 CPU CORE AND INSTRUCTION SET Table 9-1 MUL instruction X:A X*A Multiplies the eight bits in the index register by the eight bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. ...
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... Addressing modes Bit test and branch 2• 01+2• MC68HC05BD3 TPG ...
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... Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-operation Stop Wait MC68HC05BD3 CPU CORE AND INSTRUCTION SET Addressing modes Inherent Inherent Direct (A) ( ...
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... Condition code symbols Tested and set if true, cleared otherwise • Not affected ? Load CCR from stack 0 Cleared 1 Set MC68HC05BD3 TPG ...
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... DIR Direct IX1 Indexed, 1 byte offset EXT Extended IX2 Indexed, 2 byte offset INH Inherent REL Relative Not implemented MC68HC05BD3 CPU CORE AND INSTRUCTION SET Addressing modes EXT REL IX IX1 IX2 BSC BTB Condition code symbols H Half carry (from bit 3) I Interrupt mask ...
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... Table 9-8 M68HC05 opcode map CPU CORE AND INSTRUCTION SET TPG MC68HC05BD3 ...
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... In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. Address bus high MC68HC05BD3 CPU CORE AND INSTRUCTION SET HMOS/M146805 CMOS EA = PC+1 ...
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... Address bus high where K = the carry from the addition of X and (PC+2) 9- (PC+1):(PC+2); PC (PC+1); Address bus low PC+1 Address bus high 0; Address bus low EA = X+(PC+1); PC PC+2 K; Address bus low EA = X+[(PC+1):(PC+2)]; PC (PC+1)+K; Address bus low CPU CORE AND INSTRUCTION SET PC+3 (PC+2) X X+(PC+1) PC+3 X+(PC+2) MC68HC05BD3 TPG ...
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... The span of branch is from –125 to +130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. Address bus high EA2 = PC+3+(PC+2); PC MC68HC05BD3 CPU CORE AND INSTRUCTION SET EA if branch taken; otherwise PC (PC+1) ...
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... THIS PAGE LEFT BLANK INTENTIONALLY 9 9-14 CPU CORE AND INSTRUCTION SET TPG MC68HC05BD3 ...
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... NOP instruction by the CPU ever encountered. The flow of the WAIT mode is shown in Figure 10-1. 10.1 STOP Mode Stop mode is not implemented on the MC68HC05BD3. The STOP instruction will be treated and executed as a NOP instruction. Therefore, the I-bit in the Condition Code register will not be cleared. 10.2 ...
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... COP Watchdog Timer Considerations The COP watchdog timer is always enabled in MC68HC05BD3. It will reset the MCU when it times out. For a system that must have intentional uses of the WAIT Mode, care must be taken to prevent such situations from happening during normal operations by arranging timely interrupts to reset the COP watchdog timer ...
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... OPERATING MODES The MC68HC05BD3/MC68HC05BD5/ MC68HC705BD3 MCU has two modes of operation, the User Mode and the Self-Check/ Bootstrap Mode. Figure 11-1 shows the flowchart of entry to these two modes, and Table 11-1 shows operating mode selection. RESET PB5 = V SELF-CHECK/ BOOTSTRAP MODE Figure 11-1 Flowchart of Mode Entering ...
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... Self-Check Mode The self-check mode is provided on the MC68HC05BD3 and MC68HC05BD5 for the user to check device functions with an on-chip self-check program masked at location $3F00 to $3FDF under minimum hardware support. The hardware is shown in Figure 11-3. Figure 11-2 is the criteria to enter self-check mode, where PB5’s condition is latched within first two clock cycles after the rising edge of the reset ...
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... RESET + 2 4K7 + Figure 11-3 MC68HC05BD3 Self-Test Circuit MC68HC05BD3 8 x 4K7 IRQ 10K PD0/SDA PC0/PWM8 PC1/PWM9 PD1/SCL PC2/PWM10 VSYNC PC3/PWM11 HSYNC PC4/PWM12 PC5/PWM13 XTAL PC6/PWM14/VTTL PC7/PWM15/HTTL EXTAL MC68HC05BD3 20p PA0 PA1 ...
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... Refer to Section 15 for further details on MC68HC705BD3. 11 11-4 Table 11-2 Self-Check Report PB3 PB1 PB0 REMARKS Flashing O.K. (self-check is on-going Bad I BAD RAM BAD ROM BAD IRQ 1=LED off, 0=LED on for any other reset. The user EPROM consists of 7.75K-bytes, RL OPERATING MODES TPG MC68HC05BD3 ...
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... ELECTRICAL SPECIFICATIONS This section contains the electrical specifications for MC68HC05BD3. 12.1 Maximum Ratings (Voltages referenced RATINGS Supply Voltage Input Voltage IRQ Current Drain per pin excluding V DD Operating Temperature Storage Temperature Range This device contains circuitry to protect the inputs against damage due to high static voltages or electric fi ...
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... DC Electrical Characteristics Table 12-1 DC Electrical Characteristics for MC68HC05BD3 (V =5.0Vdc 10 CHARACTERISTICS Output voltage I = –10 A LOAD I = +10 A LOAD Output high voltage (I PA0-PA7, PB0-PB1, PC6-PC7, PD0-PD1 Output low voltage (I LOAD PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, PWM0-PWM7 Input high voltage PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, IRQ, RESET, EXTAL ...
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... External RESET pulse width Watchdog RESET output pulse width Watchdog time-out Interrupt pulse width (edge-triggered) Interrupt pulse period EXTAL pulse width Notes: (1) The minimum period t ILIL interrupt service routine plus 21 t MC68HC05BD3 ELECTRICAL SPECIFICATIONS Table 12-2 Control Timing SYMBOL MINIMUM – f OSC dc /2) ...
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... CYC 4 – t CYC 250 – – t CYC 2 – t CYC 2 – t CYC MINIMUM MAXIMUM UNIT 8 – t CYC 11 – t CYC 11 – t CYC – – 300 ns t – t – ns LOW CYC 1 – t CYC 10 – t CYC 10 – t CYC t t SU.STA SU.STO MC68HC05BD3 TPG ...
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... Free-running HTTL output sync pulse (SOUT clear) Free-running HTTL output period (SOUT clear) Inserted HTTL sync pulse (INSRT cleared) Inserted HTTL period error (INSRT cleared) VSYNC to VTTL delay (8pF loading) HSYNC to HTTL delay (8pF loading) HSYNC to VTTL delay (composite sync) MC68HC05BD3 ELECTRICAL SPECIFICATIONS SYMBOL MINIMUM MAXIMUM UNIT t ...
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... THIS PAGE LEFT BLANK INTENTIONALLY 12 12-6 ELECTRICAL SPECIFICATIONS TPG MC68HC05BD3 ...
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... MECHANICAL SPECIFICATIONS This section provides the mechanical dimension for the 42-pin SDIP and 40-pin DIP packages for the MC68HC05BD3. 13.1 42-Pin SDIP Package (Case 858-01 13.2 40-Pin DIP Package (Case 711-03 MC68HC05BD3 MECHANICAL SPECIFICATIONS 13 22 -B- 21 ...
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... THIS PAGE LEFT BLANK INTENTIONALLY 13 13-2 MECHANICAL SPECIFICATIONS TPG MC68HC05BD3 ...
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... MC68HC705BD3 The MC68HC705BD3 is functionally equivalent to MC68HC05BD3, but with increased RAM size to 256 bytes and the user ROM is replaced by an 7.75K-bytes user EPROM (located from $2000 to $3EFF). The entire MC68HC05BD3 data sheet applies to the MC68HC705BD3, with exceptions outlined in the section. 14.1 Features • ...
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... Unused $12 Unused $13 Unused $14 Unused $15 Unused $16 $17 $19 $1A $1B Unused $1C $1D $1E Reserved $1F PWM0 $20 PWM1 $21 PWM2 $22 PWM3 $23 PWM4 $24 PWM5 $25 PWM6 $26 PWM7 $27 PWM8 $28 PWM9 $29 PWM10 $2A PWM11 $2B PWM12 $2C PWM13 $2D PWM14 $2E PWM15 $2F Reserved Reserved MFT MBUS SSP IRQ SWI RESET MC68HC05BD3 TPG ...
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... CLR PCR ;reset PCR LDX #$00 ;load index register with 00 BSET 1,PCR ;set ELAT bit LDA #$00 ;load data= STA $2000,X ;latch data and address MC68HC05BD3 bit 5 bit 4 bit 3 bit 2 bit 1 ELAT voltage is applied to the MC68HC705BD3 State bit 0 on reset PGM ---- --00 pin ...
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... V V -0.8 – – – – 0.4 V 0.7xV – 2.0 – – V 0.2xV – V 0.8 SS – – – – – – – – – – =4.2MHz), OSC =20pF on EXTAL. L – 0.2 Vdc. MC68HC05BD3 TPG ...
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... MC68HC05BD5 The MC68HC05BD5 is functionally equivalent to MC68HC05BD3, but with increased RAM size of 256 bytes and ROM size of 7.75K-bytes. The entire MC68HC05BD3 data sheet applies to the MC68HC05BD5, with exceptions outlined in the section. 15.1 Features • Functionally equivalent to MC68HC05BD3 • 256 bytes on-chip RAM • ...
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... Unused $12 Unused $13 Unused $14 Unused $15 Unused $16 $17 $19 $1A $1B Unused $1C Reserved $1D $1E Reserved $1F PWM0 $20 PWM1 $21 PWM2 $22 PWM3 $23 PWM4 $24 PWM5 $25 PWM6 $26 PWM7 $27 PWM8 $28 PWM9 $29 PWM10 $2A PWM11 $2B PWM12 $2C PWM13 $2D PWM14 $2E PWM15 $2F Reserved Reserved MFT MBUS SSP IRQ SWI RESET MC68HC05BD3 TPG ...
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... EXTAL ( all inputs 0.2 Vdc from rail loads, less than 50pF on all outputs, C (5) Wait I : all ports configured as inputs (6) Wait I is affected linearly by the EXTAL capacitance. DD MC68HC05BD3 SYMBOL MINIMUM TYPICAL V V -0.1 – – ...
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... THIS PAGE LEFT BLANK INTENTIONALLY 15 15-4 MC68HC05BD5 TPG MC68HC05BD3 ...
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GENERAL DESCRIPTION PIN DESCRIPTION AND I/O PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS MULTI-FUNCTION TIMER PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BD3 MC68HC05BD5 ...
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GENERAL DESCRIPTION 2 PIN DESCRIPTION AND I/O PORTS 3 MEMORY AND REGISTERS 4 RESETS AND INTERRUPTS 5 MULTI-FUNCTION TIMER 6 PULSE WIDTH MODULATION 7 M-BUS SERIAL INTERFACE 8 SYNC SIGNAL PROCESSOR 9 CPU CORE AND INSTRUCTION SET 10 LOW ...
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... MC68HC05BD3D/H ...