mc68hc05l28 Freescale Semiconductor, Inc, mc68hc05l28 Datasheet
mc68hc05l28
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mc68hc05l28 Summary of contents
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... HC05 MC68HC05L28 MC68HC705L28 TECHNICAL DATA MC68HC05L28/D !MOTOROLA ...
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MODES OF OPERATION AND PIN DESCRIPTIONS 16-BIT PROGRAMMABLE TIMER LIQUID CRYSTAL DISPLAY DRIVER MODULE CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS INTRODUCTION MEMORY AND REGISTERS INPUT/OUTPUT PORTS CORE TIMER 2 I A/D CONVERTER RESETS AND INTERRUPTS MECHANICAL DATA ORDERING INFORMATION ...
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INTRODUCTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS 3 MEMORY AND REGISTERS 4 INPUT/OUTPUT PORTS 5 CORE TIMER 6 16-BIT PROGRAMMABLE TIMER 7 LIQUID CRYSTAL DISPLAY DRIVER MODULE C-BUS 9 A/D CONVERTER 10 RESETS AND INTERRUPTS ...
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... MC68HC05L28 MC68HC705L28 High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit All Trade Marks recognized. This document contains information on new products. Specifications and information herein are subject to change without notice. All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the Customer agrees to be bound by those Terms & ...
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Conventions Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an ...
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... CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05L28/D) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category. ...
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... Motorola Ltd., Colvilles Road, Kelvin Industrial Estate, EAST KILBRIDE, G75 8BR. GREAT BRITAIN. F.A.O. Technical Publications Manager (re: MC68HC05L28/D) – Third fold back along this line – Phone No: FAX No: – Finally, tuck this edge into opposite flap – NE PAS AFFRANCHIR NO STAMP REQUIRED TPG ...
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... TABLE OF CONTENTS Paragraph Number 1.1 Features.................................................................................................................1-1 1.2 Mask options on the MC68HC05L28.....................................................................1-3 1.2.1 Option register (OPT).......................................................................................1-3 MODES OF OPERATION AND PIN DESCRIPTIONS 2.1 Modes of operation ................................................................................................2-1 2.1.1 MC68HC05L28 modes of operation ................................................................2-2 2.1.1.1 Single chip mode........................................................................................2-2 2.1.1.2 RAM bootloader mode ...............................................................................2-2 2.1.2 MC68HC705L28 modes of operation ..............................................................2-4 2.1.2.1 EPROM bootloader mode ..........................................................................2-4 2.1.2.2 RAM bootloader mode ...............................................................................2-4 2.2 Pin descriptions .....................................................................................................2-6 2.2.1 VDD and VSS ..................................................................................................2-6 2 ...
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... Computer operating properly (COP) watchdog timer ............................................5-3 5.3 Core timer registers ...............................................................................................5-3 5.3.1 Core timer control and status register (CTCSR)..............................................5-3 5.3.2 Core timer counter register (CTCR).................................................................5-5 5.4 Core timer during WAIT .........................................................................................5-5 5.5 Core timer during STOP ........................................................................................5-5 MOTOROLA ii TITLE 3 4 INPUT/OUTPUT PORTS 5 CORE TIMER TABLE OF CONTENTS Page Number TPG MC68HC05L28 ...
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... LCD during WAIT mode.........................................................................................7-8 2 8.1 I C-bus features.....................................................................................................8-1 2 8.2 I C-bus system configuration.................................................................................8-2 2 8.3 I C-bus protocol.....................................................................................................8-2 8.3.1 START signal ...................................................................................................8-2 8.3.2 Transmission of the slave address ...................................................................8-2 8.3.3 Data transfer ....................................................................................................8-4 8.3.4 STOP signal .....................................................................................................8-4 8.3.5 Repeated START signal...................................................................................8-4 8.3.6 Arbitration procedure .......................................................................................8-4 MC68HC05L28 TITLE C-BUS TABLE OF CONTENTS Page Number TPG MOTOROLA iii ...
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... RESETS AND INTERRUPTS 10.1 Resets .................................................................................................................10-1 10.1.1 Power-on reset...............................................................................................10-1 10.1.2 RESET pin .....................................................................................................10-1 10.1.3 Computer operating properly (COP) reset.....................................................10-2 10.2 Interrupts .............................................................................................................10-2 10.2.1 Non-maskable software interrupt (SWI).........................................................10-3 10.2.2 Maskable hardware interrupts........................................................................10-3 10.2.2.1 External interrupt (IRQ0, IRQ1, IRQ2) .....................................................10-5 10.2.2.2 Real time and core timer (CTIMER) interrupts.........................................10-7 MOTOROLA iv TITLE 9 A/D CONVERTER 10 TABLE OF CONTENTS Page Number TPG MC68HC05L28 ...
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... Indexed, 8-bit offset........................................................................................11-12 11.3.7 Indexed, 16-bit offset......................................................................................11-12 11.3.8 Relative ..........................................................................................................11-13 11.3.9 Bit set/clear ....................................................................................................11-13 11.3.10 Bit test and branch .........................................................................................11-13 ELECTRICAL SPECIFICATIONS 12.1 Maximum ratings .................................................................................................12-1 12.2 Thermal characteristics and power considerations..............................................12-2 12.3 DC electrical characteristics for 5V operation......................................................12-3 12.4 AC electrical characteristics for 5V operation ......................................................12-4 12.5 A/D converter characteristics...............................................................................12-5 MC68HC05L28 TITLE 11 12 TABLE OF CONTENTS Page Number TPG MOTOROLA v ...
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... EPROM bootloader mode............................................................................... A-2 A.2.3 RAM bootloader mode.................................................................................... A-4 A.3 VPP ...................................................................................................................... A-4 A.4 EPROM programming register (PCR) .................................................................. A-5 A.4.1 ELAT — EPROM latch control ........................................................................ A-5 A.4.2 PGM — EPROM program control................................................................... A-5 A.5 Pin configurations — 56-pin SDIP ........................................................................ A-6 A.6 Ordering information............................................................................................. A-6 MOTOROLA vi TITLE 13 MECHANICAL DATA 14 A MC68HC705L28 TABLE OF CONTENTS Page Number TPG MC68HC05L28 ...
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... Electrical model of an A/D input pin........................................................................9-6 10-1 Interrupt flow chart................................................................................................10-4 11-1 Programming model .............................................................................................11-1 11-2 Stacking order ......................................................................................................11-2 12-1 Equivalent test load ..............................................................................................12-2 13-1 56-pin SDIP pinout for the MC68HC05L28/ MC68HC705L28...............................13-1 13-2 Mechanical dimensions for 56-pin SDIP...............................................................13-2 A-1 MC68HC705L28 EPROM programming circuit ..................................................... A-3 A-2 56-pin SDIP pinout for the MC68HC705L28 ......................................................... A-6 MC68HC05L28 TITLE LIST OF FIGURES ...
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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA viii LIST OF FIGURES TPG MC68HC05L28 ...
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... LIST OF TABLES Table Number 2-1 MC68HC05L28 operating mode entry conditions ..................................................2-1 MC68HC705L28 operating mode entry conditions ................................................2-1 2-2 2-3 RAM bootloader mode jump vector (MC68HC05L28)............................................2-3 RAM bootloader mode jump vectors (MC68HC705L28) ........................................2-3 2-4 3-1 Erase mode select..................................................................................................3-3 3-2 Register outline.......................................................................................................3-6 4-1 I/O pin states ..........................................................................................................4-1 4-2 I/O configuration functions......................................................................................4-4 5-1 Minimum COP reset times......................................................................................5-3 5-2 Example RTI periods ..............................................................................................5-4 7-1 LCD RAM organization ...
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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA x LIST OF TABLES TPG MC68HC05L28 ...
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... The MC68HC705L28 is an EPROM equivalent version of the MC68HC05L28, with 8K of EPROM instead ROM. All references to the MC68HC05L28 apply equally to the MC68HC705L28, unless otherwise noted. References specific to the MC68HC705L28 are italicized in the text and also, for quick reference, they are summarised in Appendix A ...
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... Power saving STOP and WAIT modes • Available in 56-pin SDIP package OSC1 OSC2 RESET IRQ0 IRQ1 IRQ2 VDD VSS Figure 1-1 MC68HC05L28/ MC68HC705L28 block diagram MOTOROLA 1-2 8176 x 8 user ROM or 256 x 8 RAM 8128 x 8 user EPROM 240 x 8 Oscillator bootstrap ROM Core timer ...
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... Mask options on the MC68HC05L28 There is only one mask option on the MC68HC05L28. This is to enable or disable the STOP instruction programmed during manufacture and must be specified on the order form. 1.2.1 Option register (OPT) In addition to its mask option, the MC68HC05L28 also has two functions that are programmable via an options register (OPT) ...
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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 1-4 INTRODUCTION TPG MC68HC05L28 ...
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... Modes of operation The MC68HC05L28 has two modes of operation available to the user – single chip and RAM bootloader. The MC68HC705L28 also has two modes of operation – single chip and EPROM/RAM bootloader. Table 2-1 and Table 2-2 show the conditions required to enter each mode on the rising edge of RESET ...
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... Single chip mode This is the normal operating mode of the MC68HC05L28 and the MC68HC705L28. In this mode the device functions as a self-contained microcomputer (MCU) with all on-board peripherals, including two 8-bit I/O ports and one 6-bit I/O port, available to the user. All address and data activity occurs within the MCU ...
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... MHz 22pF 22pF V DD 100nF All resistors are 10 k unless specified otherwise Figure 2-1 RAM bootloader circuit Table 2-3 RAM bootloader mode jump vector (MC68HC05L28) Table 2-4 RAM bootloader mode jump vectors (MC68HC705L28) MC68HC05L28 MODES OF OPERATION AND PIN DESCRIPTIONS IRQ/VPP OSC1 ...
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... VERF LED lights up. When finished programming, the PROG LEG turns off. If the MC68HC705L28 memory contents are the same as the EPROM the VERF LED lights up, otherwise no LEDs are turned on. Note: The EPROM must be erased before performing a program cycle. 2.1.2.2 RAM bootloader mode See Section 2.1.1.2. MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-4 TPG MC68HC05L28 ...
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... PB2 PB3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 VREFL PA7 ADIN VPP IRQ0/VPP VSS MHz 22pF 22pF Figure 2-2 MC68HC705L28 EPROM programming circuit MC68HC05L28 MODES OF OPERATION AND PIN DESCRIPTIONS +5V clock clear +5V S3 +5V VCC VPP PGM S2 RST ...
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... Schmitt trigger as part of its input to improve noise immunity. This interrupt can be enabled/disabled independently. 2.2.4 IRQ2 This interrupt has a software option which offers four types of interrupt triggering sensitivity. It contains an internal Schmitt trigger as part of its input to improve noise immunity. This interrupt can be enabled/disabled independently. MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-6 TPG MC68HC05L28 ...
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... OSC1 OSC2 (a) Crystal oscillator connections Figure 2-3 Oscillator connections MC68HC05L28 MODES OF OPERATION AND PIN DESCRIPTIONS ) is divided by two to give the internal OSC L OSC1 C (b) Crystal equivalent circuit MCU OSC1 External Clock (c) External clock source connections Crystal 2MHz 4MHz ...
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... RC time constant of this network is greater than the the oscillator stabilization period. A time constant of at least 100 ms is recommended MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-8 specification (see Section 12.4) does not apply when using an OXOV R C Figure 2-4 RC connection for external POR MC68HC05L28 RESET TPG MC68HC05L28 ...
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... BP0 – BP3, FP0 – FP17 These signals comprise the LCD driver subsystem. The subsystem has a maximum of 18 frontplanes and four backplanes. 2.2.10 AD0 – AD1, VREFH/VREFL These 4 signals comprise the A-to-D interface. The subsystem has a maximum of two A/D channels. MC68HC05L28 MODES OF OPERATION AND PIN DESCRIPTIONS 2 TPG MOTOROLA 2-9 ...
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... CTCSR, and memory contents remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the STOP mode only by an external interrupt or a reset (see Figure 2-5). The STOP instruction can be disabled by a mask option. When disabled executed as a NOP. MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-10 TPG MC68HC05L28 ...
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... No Figure 2-5 STOP flowchart MC68HC05L28 MODES OF OPERATION AND PIN DESCRIPTIONS STOP Stop oscillator and all clocks Clear I-bit No Reset Yes External interrupt (IRQ0,1,2) Yes Turn on oscillator Wait for time delay to stabilize 1. Fetch reset vector or 2. Service interrupt: a. stack b. set I-bit c. vector to interrupt routine ...
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... Set RESET pin to zero • Reduce the voltage on VDD. RESET must remain low during data retention mode To take the MCU out of data retention: • Return VDD to normal operating level • Return RESET to logical one. MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2- (if enabled) TPG MC68HC05L28 ...
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... WAIT Oscillator active Timer clock active Processor clocks stopped Reset Yes processor clock 1. Fetch reset vector or 2. Service interrupt: a. stack b. set I-bit c. vector to interrupt routine MC68HC05L28 MODES OF OPERATION AND PIN DESCRIPTIONS External No No interrupt (IRQ0,1,2) Yes CTimer Yes Restart internal interrupt Figure 2-6 WAIT fl ...
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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-14 TPG MC68HC05L28 ...
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... The MC68HC05L28 has a 16K byte memory map consisting of registers, user ROM, user RAM, bootstrap ROM, LCD RAM, EEPROM and I/O, as shown in Figure 3-1. 3.1 Registers All the I/O, control and status registers of the MC68HC05L28 are contained within the first 64-byte block of the memory map (address $0000 to $003F). 3.2 LCD RAM The 12 bytes of LCD RAM are located at address $0040 to $004B ...
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... Reserved $3F00 Bootstrap ROM (240 bytes) & bootstrap vectors $3FF0 User vectors (16 bytes) $3FFF Figure 3-1 Memory map of the MC68HC05L28 and MC68HC705L28 MOTOROLA 3-2 Port A data direction (DDRA) Port B data direction (DDRB) Core timer control & status (CTCSR) Core timer counter (CTCR frequency divider (MFDR) ...
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... In bulk erase mode the entire 240 bytes of EEPROM are erased. MC68HC05L28 MEMORY AND REGISTERS bit 7 bit 6 ...
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... LATCH and EEPGM cannot be set on the same write operation 3.4.2 EPROM programming register (PCR) EPROM program (PCR) MOTOROLA 3-4 to allow the RC oscillator to RCON Address bit 7 bit 6 bit 5 bit 4 $001C MEMORY AND REGISTERS State bit 3 bit 2 bit 1 bit 0 on reset ELAT PGM uuuu uu00 TPG MC68HC05L28 ...
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... Set the ELAT bit. – Write to the EPROM address. – Set the PGM bit for a time t – Clear the ELAT and PGM bits. Note: The erased state of the EPROM is $00. MC68HC05L28 MEMORY AND REGISTERS to the VPP pin apply the programming voltage. PROG ...
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... ER0 LATCH EERC EEPGM ?000 0000 ELAT PGM uuuu uu00 IRQED COPON ???? ?100 FDISP MUX4 MUX3 DISON ?000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MC68HC05L28 TPG ...
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... Reserved $002F Port D data (PORTD) $0030 Port D data direction (DDRD) $0031 Port D control (COND) $0032 Port D select (SELD) $0033 Reserved $34–$3F (1) MC68HC705L28 only MC68HC05L28 MEMORY AND REGISTERS Table 3-2 Register outline bit 6 bit 5 bit 4 bit 3 IC1IE IC2IE OC1IE TOIE CO1E IEDG1 ...
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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 3-8 MEMORY AND REGISTERS TPG MC68HC05L28 ...
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... INPUT/OUTPUT PORTS In single chip mode, the MC68HC05L28 has a total of 22 I/O lines, arranged as two 8-bit ports (A and B) and one 6-bit port (D). Each I/O line is individually programmable as either input or output, under the software control of the data direction registers. Port D shares various I/O configurations 2 with the timer and I C subsystems ...
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... The following sections explain in detail the individual bits in the data and control registers associated with the ports. MOTOROLA 4-2 DDRn Data I/O Output buffer pin O/P data buffer Input buffer Figure 4-1 Standard I/O port structure INPUT/OUTPUT PORTS DDRn DATA I/O Pin Output tristate Input 0 1 tristate 2 C subsystems. There TPG MC68HC05L28 ...
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... Reset clears these registers, thus configuring all ports as inputs. 4.4.3 Port D control register (COND) Address Port D control (COND) $0032 The select register, data direction register and control register determine the function of the I/O port, as shown in Table 4-2. MC68HC05L28 bit 7 bit 6 bit 5 bit 4 bit 3 bit 7 bit 6 ...
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... PD5/ PD4/ $0033 SCL0 SDA0 2 C clock and is always an open-drain 2 C data pin and is always an open-drain INPUT/OUTPUT PORTS State bit 3 bit 2 bit 1 bit 0 on reset PD3/ PD2/ PD1/ PD0/ 0000 0000 TCMP2 TCAP2 TCMP1 TCAP1 MC68HC05L28 TPG ...
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... This pin is configured as I/O pin PD1. PD0/TCAP1 — Port D pin 0/TCAP1 select 1 (set) – This pin is configured as timer input capture 1 input. Clearing bit 0 in the COND register enables the pull-up resistor. 0 (clear) – This pin is configured as I/O pin PD0. MC68HC05L28 INPUT/OUTPUT PORTS 4 TPG MOTOROLA 4-5 ...
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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 4-6 INPUT/OUTPUT PORTS TPG MC68HC05L28 ...
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... CORE TIMER The MC68HC05L28 has a 15-stage ripple counter called the core timer (CTIMER). Features of this timer are: timer overflow, power-on reset (POR), real time interrupt (RTI) with four selectable interrupt rates, and a computer operating properly (COP) watchdog timer. (Core timer counter) ...
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... Writing a ‘1’ has no effect. Reset clears this bit. See Section 5.3 for register details. MOTOROLA 5-2 /1024. The POR signal ( also derived from this register, at PORL 13 /2 (or f /8192), with three additional divider stages CORE TIMER /4 and can OP PORL ) of 32kHz. OP TPG MC68HC05L28 ...
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... The core timer has not overflowed. This bit is set when the core timer counter register rolls over from $FF to $00; an interrupt request will be generated if CTOFE is set. When set, the bit may be cleared by writing a ‘0’ to it. MC68HC05L28 Minimum COP reset at bus frequency: 4.194 MHz ...
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... RTI taps. SeeTable 5-2 for some example RTI periods. RT1 MOTOROLA 5-4 Table 5-2 Example RTI periods Bus frequency MHz OP RT0 Division ratio RTI period 8.2ms 16.4ms 32.8ms 65.5ms CORE TIMER Minimum COP period 57.3ms 114.7ms 229.4ms 458.8ms TPG MC68HC05L28 ...
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... The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt or an external reset, the internal oscillator will restart, followed by an internal processor stabilization delay (t ). The timer is then cleared and operation resumes. PORL MC68HC05L28 bit 7 bit 6 bit 5 bit 4 ...
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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 5-6 CORE TIMER TPG MC68HC05L28 ...
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... PROGRAMMABLE TIMER The MC68HC05L28 has a 16-bit programmable timer. This timer consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler, plus input capture/output compare circuitry. Selected input edges cause the current counter value to be latched into a 16-bit input capture register so that software can later read this value to determine when the edge occurred ...
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... PROGRAMMABLE TIMER 8 High Low High Low byte byte byte byte $24 Input capture $20 Input capture register 1 register 2 $21 $25 Edge Edge TCAP2 detect detect pin circuit 2 TCAP1 pin D Q TCMP2 pin CLK C TCMP1 D Q pin CLK C RESET TCR1 ($2C) TCR2 ($2D) OC2IE OLVL2 MC68HC05L28 TPG ...
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... Because the free-running counter is 16 bits preceded by a fixed divide-by-four prescaler, the value in the free-running counter repeats every 262144 internal bus clock cycles. TOF is set when the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set. MC68HC05L28 16-BIT PROGRAMMABLE TIMER bit 7 bit 6 ...
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... Output compare 1 interrupt enabled. 0 (clear) – Output compare 1 interrupt disabled. MOTOROLA 6-4 Address bit 7 bit 6 bit 5 bit 4 $002C IC1IE IC2IE OC1IE TOIE CO1E IEDG1 IEDG2 OLVL1 0000 0uu0 16-BIT PROGRAMMABLE TIMER State bit 3 bit 2 bit 1 bit 0 on reset TPG MC68HC05L28 ...
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... When OLVL1 is set, a high output level will be clocked into the output level register by the next successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level that will appear on the TCMP1 pin. MC68HC05L28 16-BIT PROGRAMMABLE TIMER 6 TPG ...
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... TCMP2 pin. When clear, it will be a low level that will appear on the TCMP2 pin. Bits and 7 — unused; always read 0. MOTOROLA 6-6 Address bit 7 bit 6 bit 5 bit 4 $002D 0 0 OC2IE 0 CO2E 16-BIT PROGRAMMABLE TIMER State bit 3 bit 2 bit 1 bit 0 on reset 0 0 OLVL2 0000 0000 TPG MC68HC05L28 ...
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... No timer overflow has occurred. This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt will occur, if TOIE is set. TOF is cleared by reading the TSR and the counter low register at $29. MC68HC05L28 16-BIT PROGRAMMABLE TIMER bit 7 bit 6 ...
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... TCAP1 — Timer capture 1 This bit reflects the current status of the timer capture 1 input. Note: On the MC68HC05L28, TCAP1 is connected directly to PD0 which defaults to an input 6 with pull-up on reset. TCAP1 will be ‘1’ unless PD0 is externally driven low. TCAP2 — Timer capture 2 This bit refl ...
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... A read of the input capture register LSB ($21) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. Reset does not affect the contents of the input capture register, except when exiting STOP mode. MC68HC05L28 16-BIT PROGRAMMABLE TIMER bit 7 bit 6 ...
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... Reset does not affect the contents of the input capture register, except when exiting STOP mode. MOTOROLA 6-10 Address bit 7 bit 6 bit 5 bit 4 $0024 $0025 16-BIT PROGRAMMABLE TIMER State bit 3 bit 2 bit 1 bit 0 on reset Unaffected Unaffected TPG MC68HC05L28 ...
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... The following procedure is recommended: 1) write to output compare high 1 to inhibit further compares; 2) read the timer status register to clear OC1F (if set); 3) write to output compare low 1 to enable the output compare 1 function. MC68HC05L28 16-BIT PROGRAMMABLE TIMER bit 7 bit 6 bit 5 ...
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... However, the data register can still be used as a temporary store. MOTOROLA 6-12 Address bit 7 bit 6 bit 5 bit 4 $0026 $0027 16-BIT PROGRAMMABLE TIMER State bit 3 bit 2 bit 1 bit 0 on reset Unaffected Unaffected TPG MC68HC05L28 ...
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... The relationships between the internal clock signals, the counter contents and the status of the flag bits are shown in the following diagrams. It should be noted that the signals labelled ‘internal’ (processor clock, timer clocks and reset) are not available to the user. MC68HC05L28 16-BIT PROGRAMMABLE TIMER 6 ...
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... T11 state. Figure 6-3 Timer state timing diagram for input capture MOTOROLA 6-14 $FFFC $FFFD The counter and timer control registers are the only ones affected by power-on or external reset. $F123 $F124 $???? 16-BIT PROGRAMMABLE TIMER $FFFE $FFFF $F125 $F126 $F124 TPG MC68HC05L28 ...
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... The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000 cleare by a read of the timer status register during the internal processor clock high time, followed by a rea of the counter low register. Figure 6-5 Timer state timing diagram for timer overflow MC68HC05L28 16-BIT PROGRAMMABLE TIMER $F456 $F457 ...
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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 6-16 16-BIT PROGRAMMABLE TIMER TPG MC68HC05L28 ...
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... The M68HC05 family LCD driver module can be configured with frontplane drivers and a maximum of 4 backplane drivers. This allows a maximum of 96 LCD segments. The LCD driver module on the MC68HC05L28 supports 18 frontplanes and 4 backplanes, allowing a maximum of 72 LCD segments. Each segment is controlled by a corresponding bit in the LCD RAM. The mode of operation is determined by the values set in the LCD control register at $1E. At reset or on power-up, the drivers are confi ...
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... LCD RAM Data to be displayed on the LCD must be written into the LCD RAM. The LCD RAM is comprised of 12 bytes of RAM (in the MC68HC05L28’s memory map) at $0040 – $004B. The 96 bits in the LCD RAM correspond to the 96 segments that can be driven by the frontplane/backplane drivers. ...
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... Note: V may not exceed the positive power supply voltage V LCD Note: The V option is not available on the MC68HC05L28 or MC68HC705L28, but is LCD included here for completeness of the generic module description. Bit 6 of the LCD control register must be cleared. Bit 0, $1E Bit 6, $1E Figure 7-2 Voltage level selection 7 ...
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... FPx, example 3 V FPx, example 4 Note: In this mode V1=V2 Figure 7-3 LCD waveform with 2 backplanes, 1/2 bias MOTOROLA LIQUID CRYSTAL DISPLAY DRIVER MODULE 7 LCD LCD LCD LCD LCD LCD OFF 1 Frame TPG MC68HC05L28 ...
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... LCD V2 BP1 FPx, example LCD V2 FPx, example LCD V2 FPx, example LCD V2 FPx, example Figure 7-4 LCD waveform with 2 backplanes, 1/3 bias MC68HC05L28 LIQUID CRYSTAL DISPLAY DRIVER MODULE ON OFF 1 Frame 7 TPG MOTOROLA 7-5 ...
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... DD LCD V2 BP1 LCD V2 BP2 LCD V2 FPx, example LCD V2 FPx, example LCD V2 FPx, example MOTOROLA LIQUID CRYSTAL DISPLAY DRIVER MODULE 7-6 Figure 7-5 LCD waveform with 3 backplanes ON OFF 1 Frame TPG MC68HC05L28 ...
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... LCD V2 BP2 LCD V2 BP3 LCD V2 FPx, example LCD V2 FPx, example LCD V2 FPx, example Figure 7-6 LCD waveform with 4 backplanes MC68HC05L28 LIQUID CRYSTAL DISPLAY DRIVER MODULE ON OFF 1 Frame 7 TPG MOTOROLA 7-7 ...
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... LCD control register LCD control register (LCD) VLCDON — LCD voltage select The V option is not available on the MC68HC05L28 or MC68HC705L28, therefore, this bit must LCD be cleared. FDISP — Display frequency 1 (set) – An extra divide by two stage is included in the LCD clock generator to give a reduced frame rate. For example, in the 3-way multiplexing mode, a frame rate of 45.5 Hz instead can be achieved. 0 (clear) – ...
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... Calling address identification interrupt • Generates/detects the START or STOP signal • Repeated START signal generation • Generates/recognizes the acknowledge bit • Bus busy detection MC68HC05L28 C-BUS 2 C-bus minimizes the need for large numbers of 2 C-bus is limited only C-bus control register (MCR) ...
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... STOP or repeated start). Only the slave with the calling address that matches the one transmitted by the master responds by sending back an acknowledge bit. This is done by pulling the SDA low at the ninth clock (see Figure 8-1). MOTOROLA 8 C-BUS TPG MC68HC05L28 ...
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... Figure 8-1 I MC68HC05L28 2 C bus transmission signal diagrams 2 I C-BUS 8 TPG MOTOROLA 8-3 ...
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... SDA outputs. The transition from master to slave mode does not generate a STOP condition in this case. At this point, the MAL bit in the I (MSR) is set by hardware to indicate loss of arbitration. MOTOROLA 8-4 2 C-bus status register 2 I C-BUS TPG MC68HC05L28 ...
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... SCL low after the completion of one byte of data transfer (nine bits). In such cases, it halts the bus clock and forces the master clock into a wait state until the slave releases the SCL line. MC68HC05L28 Start counting high period Wait ...
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... C-bus, and are used in slave mode in conjunction with Address bit 7 bit 6 bit 5 bit 4 MBC4 MBC3 MBC2 MBC1 MBC0 uuu0 0000 2 I C-BUS State bit 3 bit 2 bit 1 bit 0 on reset 0000 000 u State bit 3 bit 2 bit 1 bit 0 on reset 2 C-bus ranges from TPG MC68HC05L28 ...
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... MIEN — I C-bus interrupt enable 2 1 (set) – I C-bus interrupt is requested when MIF is set (clear) – I C-bus interrupt is disabled. MC68HC05L28 2 C-bus prescaler MCB4-0 Divider MCB4 352 384 ...
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... SRW bit. Writing to the MCR register clears this bit. MOTOROLA 8-8 Address bit 7 bit 6 bit 5 bit 4 $0013 MCF MAAS MBB MAL 2 C-bus (specified in MADR) matches the calling address C-BUS State bit 3 bit 2 bit 1 bit 0 on reset SRW MIF RXAK 1000 u001 TPG MC68HC05L28 ...
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... RXAK — Received acknowledge bit 1 (set) – No acknowledge signal has been detected at the ninth clock after the transmission of a byte of data. 0 (clear) – An acknowledge bit has been received at the ninth clock after the transmission of a byte of data. MC68HC05L28 2 C-bus C-BUS 8 TPG ...
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... C-bus address register (MADR) to define the slave address 2 C-bus control register (MCR) to enable the I ;DISABLE INTERRUPT 5,MSR,CHFLAG ;CHECK THE MBB BIT OF THE STATUS ;REGISTER SET, WAIT 2 I C-BUS State bit 3 bit 2 bit 1 bit 0 on reset 2 C-bus can be 2 C-bus TPG MC68HC05L28 ...
Page 91
... MIF bit if the interrupt function is disabled. The following is an example of a software response by a ‘master transmitter’ in the interrupt routine: ISR BCLR BRCLR BRCLR BRSET TRANSMIT LDA MC68HC05L28 ;UNTIL IT IS CLEAR 4,MCR ;SET TRANSMIT MODE 5,MCR ;SET MASTER MODE ;i.e. GENERATE START CONDITION CALLING ;GET THE CALLING ADDRESS MDR ...
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... BYTE TO BE READ RXCNT ;CHECK SECOND LAST BYTE TO BE ;READ NXMAR ;NOT LAST ONE OR SECOND LAST 3,MCR ;SECOND LAST, DISABLE ;ACKNOWLEDGEMENT TRANSMITTING NXMAR ;NXMAR 5,MCR ;LAST ONE, GENERATE STOP SIGNAL MDR ;READ DATA AND STORE RXBUF 2 I C-BUS TPG MC68HC05L28 ...
Page 93
... During WAIT mode, the I C-bus is idle, but ‘wakes up’ when it receives a valid start condition in slave mode. If the interrupt is enabled, the CPU comes out of WAIT mode after the end of a byte of transmission. MC68HC05L28 5,MCR ;ANOTHER START (RESTART) IS ;GENERATED BY 5,MCR ;THESE TWO CONSECUTIVE ...
Page 94
... Clear MIF No Master mode? Yes TX RX TX/ RX? Yes No Yes Set TXAK = 1 Generate STOP signal RTI 2 C-bus interrupt routine 2 I C-BUS A Yes Last byte to be read? No Second last byte to be read? No Generate STOP signal Read data from MDR and store TPG MC68HC05L28 ...
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... Clear MAL No MAAS = 1? Yes Yes SRW = 1? No Set TX mode Set RX mode Dummy read from Write to MDR MDR RTI Figure 8-3 Example of a typical I MC68HC05L28 A Yes Arbitration lost? No Yes MAAS = RX? TX Yes ACK from receiver next byte Switch to RX mode Dummy read from ...
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... THIS PAGE LEFT BLANK INTENTIONALLY 8 MOTOROLA 8- C-BUS TPG MC68HC05L28 ...
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... The analog to digital converter system consists of a single 8-bit successive approximation converter and a 16-channel multiplexer. There are only two A/D channels available on the MC68HC05L28. These are connected to the ADx pins of the MC68HC05L28 and the other channels are dedicated to internal reference points for test functions. The ADx pins do not have any internal output driver circuitry connected to them because this circuitry would load the analog input signal due to output buffer leakage current ...
Page 98
... At power-on or external reset, both the ADRC and ADON bits are cleared, thus the A/D is disabled. MOTOROLA 9-2 8-bit capacitive DAC with sample and hold Successive approximation register and control Result A/D status/control register (ADSTAT) CH0 CH1 CH2 A/D result data register (ADDATA) Figure 9-1 A/D converter block diagram A/D CONVERTER VRH VRL CH3 ADON ADRC COCO TPG MC68HC05L28 ...
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... The ADON bit allows the user to enable/disable the A/D converter. 1 (set) – A/D converter is switched on. 0 (clear) – A/D converter is switched off. When the A/D converter is switched on, it takes time t Section 12.4). During this time A/D conversion results may be inaccurate. MC68HC05L28 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 CH3 CH2 to stabilize (see Section 12 ...
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... VRH pin (high (VRH + VRL VRL pin (low VRL pin (low VRL pin (low VRL pin (low VRL pin (low VRL pin (low) A/D CONVERTER Comments TPG MC68HC05L28 ...
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... A/D result data register (ADDATA) $0017 ADDATA is a read-only register which is used to store the result of an A/D conversion. The result is loaded into the register from the SAR and the conversion complete flag in the ADSTAT register, COCO, is set. MC68HC05L28 bit 7 bit 6 bit 5 bit 4 bit 3 ...
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... Analog input pin 9 Note: The analog switch is closed during the 12 cycle sample time only. Figure 9-2 Electrical model of an A/D input pin MOTOROLA 9-6 Input protection device 50k + ~20V - ~0.7V < 2pF 400 nA junction leakage A/D CONVERTER 10pF DAC capacitance V RL TPG MC68HC05L28 ...
Page 103
... RESETS AND INTERRUPTS 10.1 Resets The MC68HC05L28 can be reset in three ways: by the initial power-on reset function active low input to the RESET pin and by a COP watchdog timer reset, if the watchdog timer is enabled. 10.1.1 Power-on reset A power-on reset occurs when a positive transition is detected on VDD. The power-on reset function is strictly for power turn-on conditions and should not be used to detect drops in the power supply voltage ...
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... If interrupts are not masked (CCR I-bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Table 10-1 shows the relative priority of all the possible interrupt sources. Figure 10-1 shows the interrupt processing flow. MOTOROLA 10-2 RESETS AND INTERRUPTS TPG MC68HC05L28 ...
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... Clearing the I-bit allows interrupt processing to occur. Note: The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit is cleared. MC68HC05L28 RESETS AND INTERRUPTS Register Flags Vector Address — ...
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... Figure 10-1 Interrupt flow chart RESETS AND INTERRUPTS Stack PC Set I-bit Load PC From: SWI: $3FFC - $3FFD $3FFA - $3FFB IRQ0: IRQ1: $3FFA - $3FFB IRQ2: $3FFA - $3FFB CTimer: $3FF8 - $3FF9 $3FF6 - $3FF7 TIM16: $3FF4 - $3FF5 Restore registers from stack: CC MC68HC05L28 TPG ...
Page 107
... IRQ1 interrupts are enabled. 0 (clear) – IRQ1 interrupts are disabled. IRQ1LV, IRQ1EDG — IRQ1 interrupt sensitivity bits These two bits are used to select the sensitivity of the IRQ1 interrupt trigger according to Table 10-2. MC68HC05L28 RESETS AND INTERRUPTS bit 7 bit 6 bit 5 bit 4 bit 3 ...
Page 108
... Falling edge 0 1 Rising edge 1 0 Falling edge and low level 1 1 Rising edge and high level Address bit 7 bit 6 bit 5 bit 4 $000B IRQ2INT IRQ2ENA IRQ2LV IRQ2EDGIRQ2RSTIRQ2VAL RESETS AND INTERRUPTS State bit 3 bit 2 bit 1 bit 0 on reset ??00 0000 TPG MC68HC05L28 ...
Page 109
... All interrupts vector to the same service routine, whose start address is contained in memory locations $3FF4 and $3FF5. In WAIT mode the CPU clock halts but the timer continues to run. MC68HC05L28 RESETS AND INTERRUPTS IRQ2EDG Interrupt sensitivity ...
Page 110
... The WAIT instruction causes all processor clocks to stop, but leaves the core timer clock running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt (IRQ timer interrupt. There are no special WAIT vectors for these interrupts. 10 MOTOROLA 10 that cause an I RESETS AND INTERRUPTS 2 C interrupt when set TPG MC68HC05L28 ...
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... CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05L28. 11.1 Registers The MCU contains five registers, as shown in the programming model of Figure 11-1. The interrupt stacking order is shown in Figure 11- ...
Page 112
... The program counter is a 16-bit register, which contains the address of the next byte to be fetched. Although the M68HC05 CPU core can address 64K bytes of memory, the actual address range of the MC68HC05L28 is limited to 16K bytes. The two most significant bits of the program counter are therefore not used and are permanently set to zero. ...
Page 113
... This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 11-1. MC68HC05L28 CPU CORE AND INSTRUCTION SET 11 TPG ...
Page 114
... Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 11-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 11-8). MOTOROLA 11-4 CPU CORE AND INSTRUCTION SET TPG MC68HC05L28 ...
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... A1 with memory Arithmetic compare X CPX A3 with memory Bit test memory with A BIT A5 (logical compare) Jump unconditional JMP Jump to subroutine JSR MC68HC05L28 CPU CORE AND INSTRUCTION SET X:A X Cleared I : Not affected N : Not affected Z : Not affected C : Cleared MUL Addressing mode Cycles Bytes Opcode Inherent ...
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... Addressing modes Bit test and branch 2• 01+2• MC68HC05L28 TPG ...
Page 117
... Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-operation Stop Wait MC68HC05L28 CPU CORE AND INSTRUCTION SET Addressing modes Inherent Inherent Direct (A) ( ...
Page 118
... Condition code symbols Tested and set if true, cleared otherwise • Not affected ? Load CCR from stack 0 Cleared 1 Set MC68HC05L28 TPG ...
Page 119
... Indexed (no offset) DIR Direct IX1 Indexed, 1 byte offset EXT Extended IX2 Indexed, 2 byte offset INH Inherent REL Relative Not implemented MC68HC05L28 CPU CORE AND INSTRUCTION SET Addressing modes IX IX1 IX2 BSC BTB Condition code symbols H Half carry (from bit 3) I Interrupt mask N ...
Page 120
... MOTOROLA 11-10 Table 11-8 M68HC05 opcode map CPU CORE AND INSTRUCTION SET TPG MC68HC05L28 ...
Page 121
... In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. Address bus high MC68HC05L28 CPU CORE AND INSTRUCTION SET EA = PC+ (PC+1) ...
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... Address bus high where K = the carry from the addition of X and (PC+2) MOTOROLA 11- (PC+1):(PC+2); PC PC+3 (PC+1); Address bus low PC+1 Address bus high 0; Address bus low EA = X+(PC+1); PC PC+2 K; Address bus low EA = X+[(PC+1):(PC+2)]; PC (PC+1)+K; Address bus low CPU CORE AND INSTRUCTION SET (PC+2) X X+(PC+1) PC+3 X+(PC+2) MC68HC05L28 TPG ...
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... The span of branch is from –125 to +130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. Address bus high EA2 = PC+3+(PC+2); PC MC68HC05L28 CPU CORE AND INSTRUCTION SET EA if branch taken; otherwise PC (PC+1) ...
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... THIS PAGE LEFT BLANK INTENTIONALLY 11 MOTOROLA 11-14 CPU CORE AND INSTRUCTION SET TPG MC68HC05L28 ...
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... Supply voltage Input voltage: Normal operations Bootloader mode (IRQ0 pin only) Current sink into port B Operating temperature range MC68HC05L28 (standard) Storage temperature range (2) Current drain per pin – excluding VDD and VSS (1) All voltages are with respect to V (2) Maximum current drain per pin is for one pin at a time, limited by an external resistor. ...
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... --------------------- - D T 273 + 273 = + + and 3.26k 2.38k 50pF Figure 12-1 Equivalent test load ELECTRICAL SPECIFICATIONS Value Unit TBD C (at equilibrium) D can be obtained for any value 4 Test Point C R1 MC68HC05L28 [1] [2] [3] A TPG ...
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... V from rail loads; maximum load on outputs 50pF OSC (20pF on OSC2). STOP and WAIT I STOP I : measured with OSC1 = V DD (4) Values are guaranteed, but not tested. MC68HC05L28 ELECTRICAL SPECIFICATIONS = – +85 C, unless otherwise stated) A (1) Symbol Min Typ ...
Page 128
... MHz 460 — ns — 100 ms — 100 ms 1.5 — CYC 250 — ns — — t CYC t 90 — — ms 100 — ms 400 — — ms — CYC 250 — ns (3) — t CYC ) this is the limiting factor in determining MC68HC05L28 TPG ...
Page 129
... IN REF Sample time Input capacitance Analog input voltage (1) This figure includes quantization noise (2) A/D accuracy may decrease proportionally as V (3) TAD = T if the clock source is the same as the MCU CYC (4) Inherently guaranteed by the design MC68HC05L28 ELECTRICAL SPECIFICATIONS Min Max 8 8 — 1.5 V – 0 0.1 ...
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... THIS PAGE LEFT BLANK INTENTIONALLY 12 MOTOROLA 12-6 ELECTRICAL SPECIFICATIONS TPG MC68HC05L28 ...
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... VSS VDD IRQ2 IRQ1 VPP /IRQ0 RESET OSC1 OSC2 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 Figure 13-1 56-pin SDIP pinout for the MC68HC05L28/ MC68HC705L28 MC68HC05L28 PB7 2 55 PB6 3 54 PB5 4 53 PB4 5 52 PB3 6 51 ...
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... Dimensions A, A1 and L are measured with the package seated in Jedec seating plane gauge GS-3. 6. This package conforms to EIAJ reference SC-553-64B. MECHANICAL DATA ø Seating L Plane A 1 Dim. Min. Max. e 1.78 BSC 1 e 19.05 BSC A L 3.05 3.43 ø 1. 1.19 1.45 MC68HC05L28 TPG ...
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... ORDERING INFORMATION This section describes the information needed to order the MC68HC05L28 or MC68HC705L28 . To initiate a ROM pattern for the MCU necessary to contact your local field service office, local sales person or Motorola representative. Please note that you will need to supply details such as: ...
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... C) and at 5 Volts. These RVUs are included in the mask charge and are not production parts. They are neither backed nor guaranteed by Motorola Quality Assurance. 14 MOTOROLA 14-2 ORDERING INFORMATION TPG MC68HC05L28 ...
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... This appendix summarises the differences between the MC68HC05L28 and the MC68HC705L28. The same information can also be found in appropriate sections of the book. The MC68HC705L28 is an EPROM version of the MC68HC05L28. The 8176 bytes of user ROM in the MC68HC05L28 are replaced by 8128 bytes of user EPROM. ...
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... EPROM contents are compared to that of the external EPROM and, if they match exactly, the VERF LED lights up. When finished programming, the PROG LEG turns off. If the MC68HC705L28 memory contents are the same as the EPROM the VERF LED lights up, otherwise no LEDs are turned on. 15 MOTOROLA A-2 MC68HC705L28 TPG MC68HC05L28 ...
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... TCAP1 TCAP2 VREFH PB2 PB3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 VREFL PA7 ADIN VPP IRQ0/VPP VSS MHz 22pF 22pF Figure A-1 MC68HC705L28 EPROM programming circuit MC68HC05L28 +5V clock clear +5V S3 +5V VCC VPP PGM S2 RST ...
Page 138
... Table A-2 MC68HC705L28 bootloader mode jump vectors A.3 VPP The VPP pin is the voltage input for the EPROM in both read and programming modes. 15 MOTOROLA A-4 Address Pseudo-vector 0083 Software interrupt 0086 IRQ 0089 Core timer 2 008C I C-bus 008F 16 bit timer MC68HC705L28 TPG MC68HC05L28 ...
Page 139
... Apply the programming voltage V – Set the ELAT bit. – Write to the EPROM address. – Set the PGM bit for a time t – Clear the ELAT and PGM bits. Note: The erased state of the EPROM is $00. MC68HC05L28 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 to the VPP pin ...
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... BP1 FP5 22 35 BP0 FP6 23 34 FP17 FP7 24 33 FP16 FP8 25 32 FP15 FP9 26 31 FP14 FP10 27 30 FP13 FP11 28 29 FP12 Table A-3 MC68HC705L28 order numbers Package type Temperature 56-pin SDIP (OTP +70 C MC68HC705L28 Part number MC68HC705L28B TPG MC68HC05L28 ...
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... Electrostatic discharge. Expanded mode In this mode the internal address and data bus lines are connected to external pins. This enables the device to be used in much more complex systems, where there is a need for external memory for example. MC68HC05L28 GLOSSARY GLOSSARY TPG MOTOROLA ...
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... Plastic leaded chip carrier package. PLL Phase-locked loop circuit. This provides a method of frequency multiplication, to enable the use of a low frequency crystal in a high frequency circuit. Prebyte This byte is sometimes required to qualify an opcode, in order to fully specify a particular instruction. See also: opcode, operand. MOTOROLA ii GLOSSARY TPG MC68HC05L28 ...
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... A means of connecting outputs together such that the resulting composite output state is the logical OR of the state of the individual outputs. Word Two bytes; 16 bits. XIRQ Non-maskable interrupt request. The overline indicates that this has an active-low signal format. MC68HC05L28 . DD GLOSSARY TPG MOTOROLA iii ...
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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA iv GLOSSARY TPG MC68HC05L28 ...
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... ADx analog input 9-6 alternate counter registers 6-3 B bit set/clear addressing mode 11-13 bit test and branch addressing mode 11-13 block diagrams A/D converter 9-2 core timer 5-1 LCD 7-1 MC68HC05L28 1-2 MC68HC705L28 1-2 programmable timer 6-2 BP0 – BP3 2-9 MC68HC05L28 INDEX C C-bit in CCR 11-3 CCR – condition code register 11-2 CH3 – CH0 bits in ADSTAT 9-4 ...
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... IRQ1VAL – IRQ1 pin status 10-6 IRQ2 status/control register IRQ2ENA – IRQ2 interrupt enable 10-6 IRQ2INT – IRQ2 interrupt flag 10-6 IRQ2LV, IRQ2EDG – IRQ2 interrupt sensitivity 10-6 IRQ2RST – IRQ2 interrupt flag reset bit 10-7 IRQ2VAL – IRQ2 pin status 10-7 IRQED bit in OPT 1-3 J junction temperature 12-2 INDEX TPG MC68HC05L28 ...
Page 147
... MFDR — I C-bus frequency divider register 8-6 MIEN bit in MCR 8-7 MIF bit in MSR 8-9 modes of operation data retention 2-12 entry conditions 2-1 , EPROM bootloader 2-4 A-2 RAM bootloader (MC68HC05L28) 2-2 RAM bootloader (MC68HC705L28) A-4 single chip 2-2 STOP 2-10 WAIT 2-12 MC68HC05L28 2 MSR — I C-bus status register 8-8 MSTA bit in MCR 8-8 MTX bit in MCR 8-8 ...
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... R RAM 3-1 RAM (LCD) 3-1 RAM bootloader mode (MC68HC05L28) 2-2 RAM bootloader mode (MC68HC705L28) A-4 real time interrupts 5-2 register outline 3-6 relative addressing mode 11-13 RESET 2-8 resets COP 10-2 power-on 10-1 RESET pin 10-1 ...
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... X X – index register 11-2 Z Z-bit in CCR 11-3 MC68HC05L28 INDEX TPG MOTOROLA ix ...
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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA x INDEX TPG MC68HC05L28 ...
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... CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05L28/D) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category. ...
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... Motorola Ltd., Colvilles Road, Kelvin Industrial Estate, EAST KILBRIDE, G75 8BR. GREAT BRITAIN. F.A.O. Technical Publications Manager (re: MC68HC05L28/D) – Third fold back along this line – Phone No: FAX No: – Finally, tuck this edge into opposite flap – NE PAS AFFRANCHIR NO STAMP REQUIRED TPG ...
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MODES OF OPERATION AND PIN DESCRIPTIONS 16-BIT PROGRAMMABLE TIMER LIQUID CRYSTAL DISPLAY DRIVER MODULE CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS INTRODUCTION MEMORY AND REGISTERS INPUT/OUTPUT PORTS CORE TIMER 2 I A/D CONVERTER RESETS AND INTERRUPTS MECHANICAL DATA ORDERING INFORMATION ...
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INTRODUCTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS 3 MEMORY AND REGISTERS 4 INPUT/OUTPUT PORTS 5 CORE TIMER 6 16-BIT PROGRAMMABLE TIMER 7 LIQUID CRYSTAL DISPLAY DRIVER MODULE C-BUS 9 A/D CONVERTER 10 RESETS AND INTERRUPTS ...
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Literature Distribution Centres: EUROPE: Motorola Ltd., European Literature Centre, 88 Tanners Drive, Blakelands, 13 Milton Keynes, MK14 5BP, England. ASIA PACIFIC: Motorola Semiconductors (H.K.) Ltd., Silicon Harbour Center, ...