mc68hc11ea9 Freescale Semiconductor, Inc, mc68hc11ea9 Datasheet
mc68hc11ea9
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mc68hc11ea9 Summary of contents
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... Microcontrollers 1 Introduction The MC68HC11EA9 and MC68HC711EA9 microcontroller units (MCUs) are high-performance mem- bers of the M68HC11 family of MCUs. The MC68HC(7)11EA9 MCUs have a multiplexed external ad- dress and data bus and are characterized by high speed and low power consumption. Their fully static design allows operation at frequencies from 3 MHz to dc ...
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... EEPROM Security ..........................................................................................................21 5 Resets and Interrupts 6 Parallel Input/Output 7 Timing System 7.1 Phase-Locked Loop Synthesizer ............................................................................................... 32 7.2 Main Timer ................................................................................................................................34 7.3 Real-Time Interrupt ................................................................................................................... 42 7.4 Pulse Accumulator ....................................................................................................................43 8 Serial Communications Interface 9 Analog-to-Digital Converter For More Information On This Product, 2 TABLE OF CONTENTS Go to: www.freescale.com Page MC68HC11EA9 MC68HC11EA9TS/D ...
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... TI4/ Timer Input Capture 4/Output Compare .$101E–$101F . . . . . . . . 42 TIC1–TIC3 . . . . . . Timer Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1010–$1015 . . . . . . . . 42 TMSK1 . . . . . . . . . Timer Interrupt Mask .$1022 . . . . . . . . . . . . . . 43 TMSK2 . . . . . . . . . Timer Interrupt Mask .$1024 . . . . . . . . . . . 44, 51 TOC1–TOC4 . . . . . Timer Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . .$1016–$101D . . . . . . . . 42 MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Register Index Go to: www.freescale.com ...
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... IRQ/ XIRQ RESET PPEE PPE IPIN XPIN INTERRUPT LOGIC M68HC11 CPU SERIAL ADDRESS/DATA COMMUNICATION INTERFACE SCI PARALLEL I/O CONTROL CONTROL PORT D PORT C Go to: www.freescale.com 12 KBYTES ROM/EPROM 512 BYTES EEPROM 512 BYTES RAM V A/D CONVERTER PORT E EA9 BLOCK MC68HC11EA9 MC68HC11EA9TS/D ...
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... PC7/ADDR7/DATA7 16 RESET XIRQ/V PPE 19 IRQ/V PPEE 20 PD0/RxD * V APPLIES ONLY TO DEVICES WITH EPROM/OTPROM. PPE Figure 2 MC68HC(7)11EA9 PLCC/CLCC Pin Assignments MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D 46 PE5/AN5 PE1/AN1 45 44 PE4/AN4 43 PE0/AN0 42 PB0/ADDR8 PB1/ADDR9 41 40 MC68HC(7)11EA9 PB2/ADDR10 PB3/ADDR11 39 PB4/ADDR12 38 37 ...
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... PB2/ADDR10 PB3/ADDR11 15 (0.070" SPACING) PB4/ADDR12 16 41 PB5/ADDR13 PB6/ADDR14 PB7/ADDR15 PPE PPEE 21 36 PA0/IC3 PA1/IC2 23 34 PA2/IC1 24 PA3/OC5/IC4/OC1 PA4/OC4/OC1 26 XFC 31 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 Go to: www.freescale.com EA9 56-PIN DIP MC68HC11EA9 MC68HC11EA9TS/D ...
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... C 2 MHz 3 MHz – 125 C 2 MHz 3 MHz Go to: www.freescale.com MC Order Number MC68HC11EA9BCFN2 MC68HC11EA9CFN2 MC68HC11EA9CFN3 MC68HC11EA9VFN2 MC68HC11EA9VFN3 MC68HC11EA9MFN2 MC68HC11EA9MFN3 MC68HC11EA9CP2 MC68HC11EA9CP3 MC68HC11EA9VP2 MC68HC11EA9VP3 MC68HC11EA9MP2 MC68HC11EA9MP3 MC68HC711EA9CFN2 MC68HC711EA9CFN3 MC68HC711EA9VFN2 MC68HC711EA9VFN3 MC68HC711EA9MFN2 MC68HC711EA9MFN3 MC68HC711EA9CP2 MC68HC711EA9CP3 MC68HC711EA9VP2 MC68HC711EA9VP3 MC68HC711EA9MP2 MC68HC711EA9MP3 ...
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... ACCUMULATOR DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER to: www.freescale.com 0 A CCR V C CARRY OVERFLOW ZERO NEGATIVE I INTERRUPT MASK HALF CARRY (FROM BIT 3) X INTERRUPT MASK STOP DISABLE MC68HC11EA9 MC68HC11EA9TS/D ...
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... Six addressing modes can be used to access memory: immediate, direct, extended, indexed, inherent, and relative. These modes are not detailed in this manual. For a complete description of the CPU reg- isters, addressing modes, and instruction set refer to the M68HC11 Reference Manual (M68HC11RM/ AD). MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D Go to: www.freescale.com 9 ...
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... PC2 PC1 PC0 AS R to: www.freescale.com ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DATA1 Q1 ADDR7 DATA2 Q2 ADDR6 DATA3 Q3 ADDR5 DATA4 Q4 ADDR4 DATA5 Q5 ADDR3 DATA6 Q6 ADDR2 DATA7 Q7 ADDR1 DATA8 Q8 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 MC68HC11EA9 MC68HC11EA9TS/D ...
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... SMOD cannot be set once it has been cleared. Table 2 Operating Mode Selection Inputs MODA MODB MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D ), which allows RAM contents to be STBY IRVNE PSEL3 PSEL2 ...
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... INIT register. If RAM and registers are mapped to the same boundary, the first 64 bytes of RAM will be inaccessible. Table 4 shows the arrangement of control registers and bits within the register block. For More Information On This Product Clock IRV Function Out of Reset Out of Reset On Off On Off On Off to: www.freescale.com IRVNE Bit Affects Only E IRV E IRV MC68HC11EA9 MC68HC11EA9TS/D ...
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... These four bits specify the upper hexadecimal digit of the address for the 64-byte block of internal reg- isters. The register block, positioned at the beginning of any 4 Kbyte page in the memory map, is initial- ized to address $1000 out of reset. MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D 0000 EXT 01FF 1000 ...
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... OM5 OL5 TCTL1 EDG3B EDG3A TCTL2 IC2I IC3I TMSK1 IC2F IC3F TFLG1 PR1 PR0 TMSK2 0 0 TFLG2 RTR1 RTR0 PACTL 1 Bit 0 PACNT SBR9 SBR8 SCBDH SBR1 SBR0 SCBDL PE PT SCCR1 RWU SBK SCCR2 FE PF SCSR1 0 RAF SCSR2 0 0 SCDRH MC68HC11EA9 MC68HC11EA9TS/D ...
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... MC68HC711EA9 only. 2. Factory test only. 4.9 ROM/EPROM/OTPROM The MC68HC11EA9 contains 12 Kbytes of mask-programmed ROM. The ROM array is programmed at the factory to customer specifications and cannot be altered. The ROM array can be disabled by clearing the ROMON bit in the CONFIG register. The MC68HC711EA9 MCU contains 12 Kbytes of on-chip EPROM/OTPROM. When the MC68HC711EA9 is packaged in a windowed CLCC, the 12 Kbytes of EPROM may be erased by ex- posing the device to ultraviolet light ...
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... PA5/OC3/OC1 MC68HC711EA9 XTAL E EXTAL MODA/LIR MODB/V STBY RESET PB6/ADDR14 PA0/IC3 PA1/IC2 Go to: www.freescale.com GND NC NC NOTE GND GND GND NOTE 3 GND GND GND GND 7EA9 PROG CONN pin. Any operat- PPE MC68HC11EA9 MC68HC11EA9TS/D ...
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... EPROM address and data bus configured for programming BYTE — Byte/Other EEPROM Erase Mode Refer to 4.10 EEPROM. ROW — Row/All EEPROM Erase Mode Refer to 4.10 EEPROM. MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D voltage. PPE NOTE is present on the XIRQ pin, the EPROM will be programmed ...
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... Bulk erase is done by writing to any location in the array. 3. Set the ERASE, EELAT, EEPGM, and appropriate BYTE and ROW bits in PPROG register. For More Information On This Product, 18 and the frequency of the driving clock. The clock source driving the Go to: www.freescale.com uses MOS ca- DD MC68HC11EA9 MC68HC11EA9TS/D ...
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... EEPROM contents regardless of BPRT[3:0] (windowed packages only). When cleared, they allow programming and erasure of the associated block. Bit Name BPRT0 BPRT1 BPRT2 BPRT3 MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D CAUTION — PTCON BPRT3 ...
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... When the CONFIG register is read, the static latches are accessed. For More Information On This Product BYTE ROW ERASE Table 6 BYTE/ROW Control Bits ROW Action 0 Bulk Erase (All 512 Bytes) 1 Row Erase (16 Bytes) 0 Byte Erase 1 Byte Erase Go to: www.freescale.com $103B 1 BIT 0 EELAT PGM 0 1 MC68HC11EA9 MC68HC11EA9TS/D ...
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... Resident pro- grams, however, have unlimited access to the internal EEPROM and RAM and can read, write, or trans- fer the contents of these memories. MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS — ...
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... SCI Transmit Data Register Empty • SCI Transmit Complete • SCI Idle Line Detect FFD8, D9 Reserved For More Information On This Product, 22 Interrupt Source CCR Mask — Bit I — Go to: www.freescale.com Local Mask Priority (1 = High) — — 18 RIE RIE TIE TCIE ILIE — — MC68HC11EA9 MC68HC11EA9TS/D ...
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... Clock monitor disabled; slow clock can be used Slow or stopped clocks cause COP failure reset. Bit 2 — Not implemented Always reads zero CR[1:0] — COP Timer Rate Select Refer to the following table of COP timer rates. MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D Bit I Bit I Bit I Bit I Bit I Bit I Bit I ...
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... E 17 131.072 ms 65.536 524.288 ms 262.140 2.097 s 1.049 IRVNE PSEL3 PSEL2 — to: www.freescale.com 10.923 ms 43.691 ms 174.76 ms 699.05 ms $103A 1 BIT $103C 1 BIT 0 PSEL1 PSEL0 0 1 MC68HC11EA9 MC68HC11EA9TS/D ...
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... COP system enabled (forces reset on timeout COP system disabled ROMON — ROM/EPROM Enable Refer to 4 Operating Modes and On-Chip Memory. EEON — EEPROM Enable Refer to 4.10 EEPROM MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D PSEL0 Interrupt Source Promoted 0 Timer Overflow 1 Pulse Accumulator Overflow 0 ...
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... Multiplexed Low Order Address/Data — 2 — — — — XPIN (XIRQ pin configured for data input) — — IPIN (IRQ pin configured for data input) Go to: www.freescale.com Shared Functions Timer High Order Address SCI/PLL Test A/D Converter MC68HC11EA9 MC68HC11EA9TS/D ...
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... Rising edge of strobe A selected. When output handshake is selected, port C lines obey the data direction register while STRA is high, but port C is forced to output when STRA is low. INVB — Invert Strobe Active level is logic zero 1 = Active level is logic one MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS HNDS OIN ...
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... Inputs latched Normal output into PORTCL port, unaffected on any in handshake active edge modes on STRA Driven as outputs if Normal output STRA at active port, unaffected level; follows in handshake DDRC if STRA not modes at active level $1000 1 BIT 0 PA1 PA0 I I IC2 IC3 — — MC68HC11EA9 MC68HC11EA9TS/D ...
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... DDRC — Port C Data Direction BIT 7 6 DDC7 DDC6 DDC5 RESET DDC[7:0] — Data Direction for Port Corresponding pin configured for input 1 = Corresponding pin configured for output MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS DDA4 DDA3 DDA2 ...
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... PE5 PE4 PE3 PE2 to: www.freescale.com $1008 1 BIT 0 PD1 PD0 0 0 TxD RxD $1009 1 BIT 0 DDD1 DDD0 0 0 $100A 1 BIT 0 PE1 PE0 I I MC68HC11EA9 MC68HC11EA9TS/D ...
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... COP Watchdog Timeout Rates (Period Length 32.768 131.072 524.288 2.098 s Time-out Tolerance (–0 ms/+...) 32.8 ms MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D Table 12 Timer Summary Common System Frequencies 8.0 MHz 12.0 MHz 2.0 MHz 3.0 MHz 500 ns 333 ns 32.768 ms 21.845 ms 2.0 s 1.333 s 131. ...
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... XFC EXTAL PCOMP PHASE DETECT PHASE-LOCKED LOOP SYNTHESIZER ÷4 SYNCHRONIZE ÷4 WITH PH2 ÷2 Go to: www.freescale.com V DDSYN VCOUT LOOP FILTER VCO FREQUENCY DIVIDER SYNR 2(Y + 1)•( SYNY[1: SYNX[5:0] E PH2 PLLTO TO TIMER PRESCALER SCI BAUD CLOCK TO SCI MODULUS BAUD GENERATOR MC68HC11EA9 MC68HC11EA9TS/D ...
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... AUTO = 1 (automatic bandwidth control mode). This bit can be written only in special test mode Loop filter low bandwidth mode is disabled (factory test only Loop filter operates according to values of AUTO and BWC control bits MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS BWC ...
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... Figure 9 shows a detailed block diagram of the timer prescaler and the capture/compare unit. For More Information On This Product SYNY4 SYNY3 SYNY2 to: www.freescale.com $1037 1 BIT 0 SYNY1 SYNY0 1 0 MC68HC11EA9 MC68HC11EA9TS/D ...
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... TIC1 (LO) 16-BIT LATCH CLK TIC2 (HI) TIC2 (LO) CLK 16-BIT LATCH TIC3 (HI) TIC3 (LO) * REFER TO PLL BLOCK DIAGRAM. MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D TOI TCNT (HI) TCNT (LO) 16-BIT FREE RUNNING TOF COUNTER TAPS FOR RTI, COP WATCHDOG, AND PULSE ACCUMULATOR OC1I OC1F FOC1 ...
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... BIT 0 — — $100D 1 BIT 0 — — $100E–$100F 9 BIT 8 TCNT (HI) 1 BIT 0 TCNT (LO) $1010–$1015 9 BIT 8 TIC1 (HI) 1 BIT 0 TIC1 (LO) 9 BIT 8 TIC2 (HI) 1 BIT 0 TIC2 (LO) 9 BIT 8 TIC3 (HI) 1 BIT 0 TIC3 (LO) MC68HC11EA9 MC68HC11EA9TS/D ...
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... TCTL2 — Timer Control 2 BIT 7 6 EDG4B EDG4A EDG1B RESET Table 15 Input Capture Channel Configuration EDGxB EDGxA MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS ...
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... Interrupts from ICx channel disabled 1 = Edges detected on ICx pin generate interrupts For More Information On This Product OC4I I4/O5I IC1I NOTE OC4F I4/O5F IC1F to: www.freescale.com $1022 1 BIT 0 IC2I IC3I 0 0 $1023 1 BIT 0 IC2F IC3F 0 0 MC68HC11EA9 MC68HC11EA9TS/D ...
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... Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration) Bits [3:2] — Not Implemented Always read zero PR[1:0] — Timer Prescaler Select Table 16 Main Timer Prescaler Selection PR1 MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS PAII — — ...
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... PEDGE — Pulse Accumulator Input Edge Select Refer to 7.4 Pulse Accumulator. For More Information On This Product PAIF — — PEDGE — I4/ to: www.freescale.com $1025 1 BIT 0 — — $1026 1 BIT 0 RTR1 RTR0 0 0 MC68HC11EA9 MC68HC11EA9TS/D ...
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... CR[1:0] — COP Timer Rate Select Refer to 5 Resets and Interrupts Table 18 COP Timer Rate Selection CR[1:0] Selected MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D RTI Rate Selected E = 1.0 MHz E = 2.0 MHz E 8.192 ms 4.096 ms E 16.384 ms 8.192 ms E 32.768 ms 16.384 ms E 65.536 ms 32 ...
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... Maximum Interrupt Frequency E = 1.0 MHz E = 2.0 MHz E 122.070 Hz 244.141 Hz E 61.035 Hz 122.070 Hz E 30.518 Hz 61.035 Hz E 15.258 Hz 30.518 PAIF — — to: www.freescale.com E = 3.0 MHz 2.731 ms 5.461 ms 10.923 ms 21.845 3.0 MHz 366.211 Hz 183.105 Hz 91.553 Hz 45.776 Hz $1025 1 BIT 0 — — MC68HC11EA9 MC68HC11EA9TS/D ...
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... When the pulse accumulator is configured for time accumulation, an edge on the pulse accumulator input pin enables a free-running clock (E divided by 64) that drives PACNT in gated time accumulation mode. Refer to Figure 10. MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS PEDGE — ...
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... MUX DATA BUS PAEN INTERNAL DATA BUS PEDGE — I4/ to: www.freescale.com PAOVI 1 PAOVF INTERRUPT REQUESTS PAII 2 PAIF DISABLE FLAG SETTING OVERFLOW PACNT 8-BIT COUNTER ENABLE EA9 PLS ACC BLOCK $1026 1 BIT 0 RTR1 RTR0 0 0 MC68HC11EA9 MC68HC11EA9TS/D ...
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... Interrupts from edges on PAI pin are disabled 1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration) Bits [3:2] — Not Implemented Always read zero PR[1:0] — Timer Prescaler Select Refer to 7.2 Main Timer. MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS ...
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... No edge has been detected on the PAI pin edge (rising or falling, depending on configuration) has been detected on the PAI pin Bits [3:0] — Not Implemented Always read zero For More Information On This Product PAIF — — to: www.freescale.com $1025 1 BIT 0 — — MC68HC11EA9 MC68HC11EA9TS/D ...
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... SCI BAUD CLOCK 13-BIT COUNTER EXTAL ÷ MCS = 0 4XCLK ÷ MCS = 1 13-BIT COMPARE SCBDH/L SCI BAUD CONTROL Figure 11 SCI Baud Generator Circuit Diagram MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D INTERNAL PHASE 2 CLOCK (PH2) RESET SYNCHRONIZE = ÷ WITH PH2 2 Go to: www ...
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... ONLY FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC SCSR1 SCI STATUS 1 TDRE TIE TC TCIE SCCR2 SCI CONTROL 2 Go to: www.freescale.com DDD1 PIN BUFFER PD1 TxD AND CONTROL INTERNAL DATA BUS EA9 SCI TX BLOCK MC68HC11EA9 MC68HC11EA9TS/D ...
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... SCSR2 SCI STATUS 2 WAKEUP LOGIC SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Figure 13 SCI Receiver Block Diagram MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D ÷16 Rx SHIFT REGISTER DATA ( RECOVERY PARITY DETECT M SCSR1 SCI STATUS 1 RDRF RIE ...
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... Go to: www.freescale.com $1028, $1029 1 BIT 0 SBR9 SBR8 High 0 0 SBR1 SBR0 Low MHz 4545 $11C1 3333 $0D05 1666 $0682 833 $0341 416 $01A0 208 $00D0 104 $0068 52 $0034 26 $001A 13 $000D MC68HC11EA9 MC68HC11EA9TS/D ...
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... TCIE — Transmit Complete Interrupt Enable interrupts disabled 1 = SCI interrupt requested when TC status flag is set RIE — Receiver Interrupt Enable 0 = RDRF and OR interrupts disabled 1 = SCI interrupt requested when RDRF flag or the OR status flag is set MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS — M WAKE ...
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... NF set, followed by SCDR read. FE — Framing Error Set if a zero is detected where a stop bit was expected. Cleared by SCSR1 read with FE set, followed by SCDR read. For More Information On This Product IDLE to: www.freescale.com $102C 1 BIT MC68HC11EA9 MC68HC11EA9TS/D ...
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... Ninth serial data bit transmitted when SCI is configured for nine data bit operation (M = 1). Bits [5:0] — Not implemented Always read zero R/T[7:0] — Receiver/Transmitter Data Bits SCI data is double buffered in both directions. MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS — — ...
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... ADR1 A/D RESULT 1 ADR2 A/D RESULT 2 For More Information On This Product, 54 8-BIT CAPACITIVE DAC WITH SAMPLE AND HOLD REGISTER AND CONTROL ADCTL A/D CONTROL RESULT REGISTER INTERFACE ADR3 A/D RESULT 3 Figure 14 A/D Block Diagram Go to: www.freescale.com INTERNAL DATA BUS ADR4 A/D RESULT 4 EA9 A/D BLOCK MC68HC11EA9 MC68HC11EA9TS/D ...
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... INPUT PROTECTION DEVICE ANALOG INPUT PIN < THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME. Figure 16 Electrical Model of an A/D Input Pin (Sample Mode) MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS/D MSB BIT 6 BIT 5 BIT 4 BIT CYCLES ...
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... AN2 1 AN3 0 AN4 1 AN5 0 AN6 1 AN7 0 Reserved 1 Reserved 0 Reserved 1 Reserved )/ Reserved Go to: www.freescale.com $1030 1 BIT MULT = 1 ADR1 ADR2 ADR3 ADR4 ADR1 ADR2 ADR3 ADR4 — — — — ADR1 ADR2 ADR3 ADR4 MC68HC11EA9 MC68HC11EA9TS/D ...
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... A delay of approximately 4000 E-clock cycles is imposed as the MCU exits STOP mode. CME — Clock Monitor Enable Refer to 5 Resets and Interrupts. Bit 2 — Not implemented Always reads zero CR[1:0] — COP Timer Rate Select Refer to 5 Resets and Interrupts. MC68HC11EA9 For More Information On This Product, MC68HC11EA9TS ...
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... Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...