mc68hc11ea9 Freescale Semiconductor, Inc, mc68hc11ea9 Datasheet - Page 28

• Manufacturer Part Number: mc68hc11ea9
• Description: 8-bit Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

handshake
handshake
PORTA — Port A Data
28
strobed
RESET:
Simple
mode
output
Alt. Pin
input
And/or
mode
mode
Func.:
Full
Full
Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at
reset. Port pins are either driven to a specified logic level or are configured as high impedance inputs.
I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the
corresponding latches are dependent upon the electrical state of the pins during reset. In port descrip-
tions, an "I" indicates this condition. Port pins that are driven to a known logic level during reset are
shown with a value of either one or zero. Some control bits are unaffected by reset. Reset states for
these bits are indicated with a "U".
with STAF = 1
with STAF = 1
with STAF = 1
Sequence
Read PIOC
Read PIOC
Read PIOC
Clearing
then write
then read
then read
PORTCL
PORTCL
PORTCL
BIT 7
OC1
PA7
STAF
PAI
I
The timer forces the I/O state to output for each port A line associated with an en-
abled output compare. In these cases the data direction bits will not be changed,
but have no effect on these lines. The DDRA will revert to controlling data direction
when the associated timer compare is disabled. Input captures do not force either
the I/O state of the pin or the state of DDRA. To enable PA3 as fourth input capture,
set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth out-
put compare out of reset, with bit I4/O5 being cleared. If the DDA3 bit in DDRA is
set (configuring PA3 as an output), and IC4 is enabled, writes to PA3 cause edges
on the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/
O5 register is acting as IC4. PA7 drives the pulse accumulator input but also can
be configured for general-purpose I/O or output compare. DDA7 bit in DDRA reg-
ister configures PA7 for either input or output. Note that even when PA7 is config-
ured as an output, the pin still drives the pulse accumulator input.
Table 11 Strobed and Handshake Parallel I/O Control Bit Summary
OC2
OC1
HNDS OIN
PA6
6
I
0
1
1
Freescale Semiconductor, Inc.
For More Information On This Product,
X
0
1
OC3
OC1
PA5
active pulse
active pulse
5
I
active level
active level
0 = STRB
1 = STRB
0 = STRB
1 = STRB
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PLS
X
OC4
OC1
PA4
4
I
Follow
DDRC
0
1
1
0
NOTE
0
1
IC4/OC5
OC1
Active Edge
PA3
3
Port C
Driven
EGA
I
STRA
PA2
IC1
Follow
DDRC
—
2
I
Driven as outputs if
DDRC if STRA not
STRA at active
Inputs latched
Inputs latched
at active level
into PORTCL
into PORTCL
level; follows
active edge
active edge
PA1
on STRA
on STRA
IC2
—
Port B
1
on any
on any
I
MC68HC11EA9TS/D
BIT 0
PA0
IC3
—
I
MC68HC11EA9
port, unaffected
port, unaffected
Normal output
in handshake
Normal output
in handshake
STRB pulses
on writes to
PORTB
modes
Port C
modes
$1000