mc68hc705p6a Freescale Semiconductor, Inc, mc68hc705p6a Datasheet - Page 51

• Manufacturer Part Number: mc68hc705p6a
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

To prevent OCF from being set between the time it is read and the time the output compare registers are
updated, use this procedure:
8.4 Timer During Wait/Halt Mode
The CPU clock halts during the wait (or halt) mode, but the timer remains active. If interrupts are enabled,
a timer interrupt will cause the processor to exit the wait mode.
8.5 Timer During Stop Mode
In the stop mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt.
If STOP is exited by RESET, the counters are forced to $FFFC. During STOP, if at least one valid input
capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any
timer flags or wake up the MCU, but if an interrupt is used to exit stop mode, there is an active input
capture flag and data from the first valid edge that occurred during the stop mode. If reset is used to exit
stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
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1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Timer During Wait/Halt Mode
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