mc68332acpv25b1 Freescale Semiconductor, Inc, mc68332acpv25b1 Datasheet - Page 19

• Manufacturer Part Number: mc68332acpv25b1
• Description: Technical Summary 32-bit Modular Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

EXOFF — External Clock Off
FRZSW — Freeze Software Enable
FRZBM — Freeze Bus Monitor Enable
SLVEN — Factory Test Mode Enabled
SHEN[1:0] — Show Cycle Enable
SUPV — Supervisor/Unrestricted Data Space
MM — Module Mapping
IARB[3:0] — Interrupt Arbitration Field
MC68332
MC68332TS/D
This bit is a read-only status bit that reflects the state of DATA11 during reset.
This field determines what the EBI does with the external bus during internal transfer operations. A
show cycle allows internal transfers to be externally monitored. The table below shows whether show
cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict,
external peripherals must not be enabled during show cycles.
The SUPV bit places the SIM global registers in either supervisor or user data space.
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration
between interrupt requests of the same priority is performed by serial contention between IARB field bit
values. Contention must take place whenever an interrupt request is acknowledged, even when there
is only a single pending request. An IARB field must have a non-zero value for contention to take place.
If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU pro-
cesses a spurious interrupt exception. Because the SIM routes external interrupt requests to the CPU,
the SIM IARB field value is used for arbitration between internal and external interrupts of the same pri-
ority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is
%0000, which prevents SIM interrupts from being discarded during initialization.
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters con-
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are dis-
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
0 = Registers with access controlled by the SUPV bit are accessible from either the user or super-
1 = Registers with access controlled by the SUPV bit are restricted to supervisor access only.
0 = Internal modules are addressed from $7FF000 –$7FFFFF.
1 = Internal modules are addressed from $FFF000 –$FFFFFF.
tinue to run.
abled, preventing interrupts during software debug.
visor privilege level.
SHEN
00
01
10
11
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Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled,
internal activity is halted by a bus grant
Action
MOTOROLA
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