mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet

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... MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual. To locate any published errata or updates for this document, contact your Freescale sales office. © Freescale Semiconductor, Inc., 2008. All rights reserved. MPC8560EC Rev. 4.2, 1/2008 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8 3 ...

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Overview 1 Overview The following section provides a high-level overview of the MPC8560 features. functional units within the MPC8560. DDR DDR SDRAM Controller SDRAM Controller GPIO Local Bus Controller 32b Programmable IRQs Interrupt Controller CPM MPHY MCC ...

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Executes code from internal ROM or instruction RAM — 32-bit RISC architecture — Tuned for communication environments: instruction set supports CRC computation and bit manipulation. — Internal timer — Interfaces with the embedded e500 core processor through a 32-Kbyte ...

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Overview — General-purpose parallel ports—16 parallel I/O lines with interrupt capability — Supports inverse muxing of ATM cells (IMA) • 256 Kbyte L2 cache/SRAM — Can be configured as follows – Full cache mode (256-Kbyte cache). – Full memory-mapped SRAM ...

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Contiguous or discontiguous memory mapping — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions — Sleep mode support for self refresh SDRAM — Supports auto refreshing — On-the-fly power management using CKE signal — Registered DIMM ...

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Overview — Interrupts can be routed to the e500 core’s standard or critical interrupt inputs — Interrupt summary registers allow fast identification of interrupt source 2 • controller — Two-wire interface — Multiple master support 2 — Master ...

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MII management interface for control and status — Programmable CRC generation and checking — Ability to force allocation of header information and buffer descriptors into L2 cache. • OCeaN switch fabric — Four-port crossbar packet switch — Reorders packets ...

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Electrical Characteristics • System performance monitor — Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the ...

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Table 1. Absolute Maximum Ratings Characteristic DDR DRAM I/O voltage Three-speed Ethernet I/O voltage CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet,MII management, DUART, system control and power management and JTAG I/O voltage Input voltage DDR DRAM signals ...

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Electrical Characteristics If the items on line 2 must precede items on line 1, please ensure that the delay will not exceed 500 ms and the power sequence is not done greater than once per day in production environment. From ...

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Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8560. G/L/OV DD G/L/OV DD G/L/ GND – 0 GND – 0.7 V Note: t refers to the clock period associated with ...

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Electrical Characteristics Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8560 for the 3.3-V signals, respectively. Overvoltage Waveform Undervoltage Waveform Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling 2.1.4 Output Driver ...

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Power Characteristics The estimated power dissipation on the V CCB Frequency (MHz) Core Frequency (MHz) Typical Power 200 267 333 Notes: 1. The values do not include I/O supply power (OV 2. Junction temperature is a function of die ...

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Power Characteristics Table 6 provides estimated I/O power numbers for each block: DDR, PCI, Local Bus, RapidIO, TSEC, and CPM. Table 6. Estimated Typical I/O Power Consumption Interface Parameter DDR I/O CCB = 200 MHz CCB = 266 MHz CCB ...

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Table 6. Estimated Typical I/O Power Consumption (continued) Interface Parameter TDMA or TDMB Nibble mode Per channel Notes =2.5, ECC enabled, 66% bus utilization, 33% write cycles, 10pF load on data, 10pF load on address/command, 10pF DD load ...

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Clock Timing 4.2 TSEC Gigabit Reference Clock Timing Table 7 provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the MPC8560. Table 8. EC_GTX_CLK125 AC Timing Specifications Parameter/Condition EC_GTX_CLK125 frequency EC_GTX_CLK125 cycle time EC_GTX_CLK125 rise and fall time ...

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Real Time Clock Timing Table 10 provides the real time clock (RTC) AC timing specifications for the MPC8560. Parameter/Condition RTC clock high time RTC clock low time 5 RESET Initialization This section describes the AC electrical specifications for the ...

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DDR SDRAM 6 DDR SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8560. 6.1 DDR SDRAM DC Electrical Characteristics Table 13 provides the recommended operating conditions for the DDR SDRAM component(s) ...

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DDR SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR SDRAM interface. 6.2.1 DDR SDRAM Input AC Timing Specifications Table 15 provides the input AC timing specifications for the DDR SDRAM interface. Table 15. ...

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DDR SDRAM 6.2.2 DDR SDRAM Output AC Timing Specifications For chip selects MCS1 and MCS2, there will always be at least 200 DDR memory clocks coming out of self-refresh after an HRESET before a precharge occurs. This will not necessarily ...

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Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode (continued) At recommended operating conditions with GV Parameter MDQS epilogue end Notes: 1.The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional ...

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DDR SDRAM Figure 6 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] MSYNC_OUT MSYNC_IN t DDKHOV ADDR/CMD Write A0 t DDSHMH MDQS[n] t DDSHMP MDQ[x] Figure 6. DDR SDRAM Output Timing Diagram 6.2.2.2 Load Effects on Address/Command Bus Table ...

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Ethernet: Three-Speed, MII Management This section provides the AC and DC electrical characteristics for three-speed and MII management. 7.1 Three-Speed Ethernet Controller (TSEC) (10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics The electrical characteristics specified here apply to all GMII (gigabit media independent ...

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Ethernet: Three-Speed, MII Management Table 20. GMII, MII, RGMII, RTBI, and TBI DC Electrical Characteristics Parameters Supply voltage 2.5 V Output high voltage (LV = Min Output low voltage (LV = Min Input high ...

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Table 21. GMII Transmit AC Timing Specifications (continued) At recommended operating conditions with LV Parameter/Condition GTX_CLK data clock rise and fall time Notes: 1. The symbols used for timing specifications herein follow the pattern t for inputs and t (reference)(state) ...

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Ethernet: Three-Speed, MII Management Table 22. GMII Receive AC Timing Specifications (continued) At recommended operating conditions with LV Parameter/Condition RX_CLK clock rise and fall time Note: 1.The symbols used for timing specifications herein follow the pattern of t for inputs ...

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MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 7.2.2.1 MII Transmit AC Timing Specifications Table 23 provides the MII transmit AC timing specifications. Table 23. MII Transmit AC Timing Specifications At recommended ...

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Ethernet: Three-Speed, MII Management 7.2.2.2 MII Receive AC Timing Specifications Table 24 provides the MII receive AC timing specifications. Table 24. MII Receive AC Timing Specifications At recommended operating conditions with LV Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock ...

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TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. 7.2.3.1 TBI Transmit AC Timing Specifications Table 25 provides the TBI transmit AC timing specifications. Table 25. TBI Transmit AC Timing Specifications At recommended ...

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Ethernet: Three-Speed, MII Management 7.2.3.2 TBI Receive AC Timing Specifications Table 26 provides the TBI receive AC timing specifications. Table 26. TBI Receive AC Timing Specifications At recommended operating conditions with LV Parameter/Condition RX_CLK clock period RX_CLK skew RX_CLK duty ...

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RGMII and RTBI AC Timing Table 27 presents the RGMII and RTBI AC timing specifications. Table 27. RGMII and RTBI AC Timing Specifications At recommended operating conditions with LV Parameter/Condition Data to clock output skew (at transmitter) Data to ...

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Ethernet: Three-Speed, MII Management Figure 14 shows the RGMII and RTBI AC timing and multiplexing diagrams. GTX_CLK (At Transmitter) TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At PHY) Figure 14. RGMII and RTBI AC Timing and Multiplexing ...

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Table 28. MII Management DC Electrical Characteristics (continued) Parameter Input high current (OV = Max Input low current (OV = Max Note: 1.Note that the symbol this case, represents the OV ...

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Local Bus Figure 15 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 15. MII Management Interface Timing Diagram 8 Local Bus This section describes the DC and AC electrical specifications for the local bus interface ...

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Table 31. Local Bus General Timing Parameters—DLL Enabled (continued) Parameter Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock ...

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Local Bus Table 31. Local Bus General Timing Parameters—DLL Enabled (continued) Parameter Local bus clock to output high impedance for LAD/LDP Notes: 1.The symbols used for timing specifications herein follow the pattern of t for inputs and t (First two ...

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Table 32. Local Bus General Timing Parameters—DLL Bypassed (continued) Parameter Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP ...

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Local Bus Figure 16 provides the AC test load for the local bus. Output Figure 17 through Figure 22 show the local bus signals. LSYNC_IN Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] ...

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Internal launch/capture clock LCLK[n] Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 18. Local Bus Signals (DLL Bypass Mode) MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale ...

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Local Bus LSYNC_IN T1 T3 GPCM Mode Output Signals: LCS[0:7]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8560 Integrated Processor Hardware ...

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Internal launch/capture clock T1 T3 LCLK GPCM Mode Output Signals: LCS[0:7]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass ...

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Local Bus LSYNC_IN GPCM Mode Output Signals: LCS[0:7]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV ...

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Internal launch/capture clock LCLK GPCM Mode Output Signals: LCS[0:7]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV ...

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CPM Table 33. CPM DC Electrical Characteristics (continued) Characteristic Output high voltage (I = –2.0 mA) OH Output low voltage (I = 3.2 mA) OL Note: 1. This specification applies to the following pins: PA[0–31], PB[4–31], PC[0–31], and PD[4–31]. 2. ...

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Table 34. CPM Input AC Timing Specifications Characteristic COL/CRS width high (FCC) Notes: 1.Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of Serial Clock. Timings are measured at the ...

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CPM Figure 24 shows the FCC internal clock. BRG_OUT FCC Input Signals FCC Output Signals (When GFMR TCI = 0) FCC Output Signals (When GFMR TCI = 1) Figure 24. FCC Internal AC Timing Clock Diagram Figure 25 shows the ...

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Figure 27 shows the SCC/SPI external clock. Serial Clock In t NEIVKH Input Signals: SCC/SPI (See Note) Output Signals: SCC (See Note) Output Signals: SPI (See Note) Note: The clock edge is selectable on SCC and SPI. Figure 27. SCC/SPI ...

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CPM 2 Table 36 shows CPM Timing. Characteristic SCL clock frequency (slave) SCL clock frequency (master) Bus free time between transmissions Low period of SCL High period of SCL 2 Start condition setup time 2 Start condition ...

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Table 37 and Table 38 are examples of I respectively. Table 37. CPM I Characteristic SCL clock frequency (slave) SCL clock frequency (master) Bus free time between transmissions Low period of SCL High period of SCL 2 Start condition setup ...

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JTAG 10 JTAG This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8560. Table 39 provides the JTAG AC timing specifications as defined in Table 39. JTAG AC Timing Specifications (Independent of SYSCLK) At ...

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Figure 31 provides the AC test load for TDO and the boundary-scan outputs of the MPC8560. Output Figure 31. AC Test Load for the JTAG Interface Figure 32 provides the JTAG clock input timing diagram. JTAG External Clock Figure 32. ...

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I2C Figure 35 provides the test access port timing diagram. JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 35. Test Access Port Timing Diagram This section describes the DC and AC ...

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Electrical Specifications Table 41 provides the AC timing parameters for the I All values refer to V (min) and V (max) levels (see IH IL Parameter SCL clock frequency Low period of the SCL clock ...

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PCI/PCI-X Figure 37 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S 12 PCI/PCI-X This section describes the DC and AC electrical specifications for the PCI/PCI-X bus of the MPC8560. 12.1 PCI/PCI-X ...

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PCI/PCI-X AC Electrical Specifications This section describes the general AC timing parameters of the PCI/PCI-X bus of the MPC8560. Note that the SYSCLK signal is used as the PCI input clock. 66 MHz. Table 43. PCI AC Timing Specifications ...

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PCI/PCI-X Figure 16 provides the AC test load for PCI and PCI-X. Output Figure 39 shows the PCI/PCI-X input AC timing conditions. CLK Input Figure 39. PCI-PCI-X Input AC Timing Measurement Conditions Figure 40 shows the PCI/PCI-X output AC timing ...

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Table 44. PCI-X AC Timing Specifications at 66 MHz (continued) Parameter PCI-X initialization pattern to HRESET setup time HRESET to PCI-X initialization pattern hold time Notes: 1.See the timing measurement conditions in the PCI-X 1.0a Specification . 2.Minimum times are ...

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RapidIO Table 45. PCI-X AC Timing Specifications at 133 MHz (continued) Parameter HRESET to PCI-X initialization pattern hold time Notes: 1.See the timing measurement conditions in the PCI-X 1.0a Specification . 2.Minimum times are measured at the package pin (not ...

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Table 46. RapidIO 8/16 LP-LVDS Driver DC Electrical Characteristics (continued) At recommended operating conditions with OV Characteristic Common mode offset voltage Differential termination Short circuit current (either output) Bridged short circuit current Notes: 1.Bridged 100-Ω load. 2.See Figure 41(a). 3.Differential ...

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RapidIO Figure 41 shows the DC driver signal levels – –V + ΔV OD –V –V – ΔV OD Differential Specifications Note: V refers to voltage at output 13.2 ...

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The peak differential signal of the transmitter output or receiver input – B volts. The peak-to-peak differential signal of the transmitter output or receiver input × (A – B) volts. • ...

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RapidIO –Y – minimum data valid amplitude Z = maximum amplitude unit interval = 1/baud rate X1 = end of zero crossing region X2 = beginning of data valid window ...

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Table 48. RapidIO Driver AC Timing Specifications—500 Mbps Data Rate (continued) Characteristic Duty cycle V rise time, 20%–80% of peak-to-peak OD differential signal swing V fall time, 20%–80% of peak-to-peak OD differential signal swing Data valid Skew of any two ...

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RapidIO Table 50. RapidIO Driver AC Timing Specifications—1 Gbps Data Rate Characteristic Differential output high voltage Differential output low voltage Duty cycle V rise time, 20%–80% of peak to peak OD differential signal swing V fall time, 20%–80% of peak ...

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The eye pattern for a data signal is generated by making a large number of recordings of the signal and then overlaying the recordings. The number of recordings used to generate the eye shall be large enough that further increasing ...

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RapidIO 13.3.2 RapidIO Receiver AC Timing Specifications The RapidIO receiver AC timing specifications are provided in specifications for each data rate/frequency for which operation of the receiver is specified. Unless otherwise specified, these specifications are subject to the following conditions. ...

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Table 53. RapidIO Receiver AC Timing Specifications—1 Gbps Data Rate Characteristic Duty cycle of the clock input Data valid Allowable static skew between any two data inputs within a 8-/9-bit group Allowable static skew of data inputs to associated clock ...

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RapidIO enough that increasing the length of the sequence does not cause the resulting eye pattern to change from one that complies with the RapidIO receive mask to one that does not comply with the mask. The data carried by ...

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Figure 48 shows the definitions of the data to clock static skew parameter t window parameter DV. The data and frame bits are those that are associated with the clock. The figure applies for all zero-crossings of the clock. All ...

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Package and Pin Listings 14 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. 14.1 Package Parameters for the MPC8560 FC-PBGA The package parameters are as provided in the following list. The package type is 29 ...

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Mechanical Dimensions of the MPC8560 FC-PBGA Figure 50 the mechanical dimensions and bottom surface nomenclature of the MPC8560, 783 FC-PBGA package. Figure 50. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8560 FC-PBGA 1. All dimensions are in millimeters. ...

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Package and Pin Listings 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls. 5. Capacitors may not be present on all devices. 6. ...

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Table 54. MPC8560 Pinout Listing (continued) Signal MDQ[0:63] M26, L27, L22, K24, M24, M23, K27, K26, K22, J28, F26, E27, J26, J23, H26, G26, C26, E25, C24, E23, D26, C25, A24, D23, B23, F22, J21, G21, G22, D22, H21, E21, ...

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Package and Pin Listings Table 54. MPC8560 Pinout Listing (continued) Signal LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LDP[0:3] LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/ LPBSE LGPL5 LSYNC_IN LSYNC_OUT LWE[0:1]/LSDDQM[0:1]/LBS [0:1] LWE[2:3]/LSDDQM[2:3]/LBS [2:3] DMA_DREQ[0:1] DMA_DACK[0:1] DMA_DDONE[0:1] MCP UDE IRQ[0:7] AA18, Y18, AB18, AG24, AA21, Y19, AA19, ...

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Table 54. MPC8560 Pinout Listing (continued) Signal EC_GTX_CLK125 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_TXD[7:4] TSEC1_TXD[3:0] TSEC1_TX_EN TSEC1_TX_ER TSEC1_TX_CLK TSEC1_GTX_CLK TSEC1_CRS TSEC1_COL TSEC1_RXD[7:0] TSEC1_RX_DV TSEC1_RX_ER TSEC1_RX_CLK Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_TXD[7:2] TSEC2_TXD[1:0] TSEC2_TX_EN TSEC2_TX_ER TSEC2_TX_CLK TSEC2_GTX_CLK TSEC2_CRS TSEC2_COL ...

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Package and Pin Listings Table 54. MPC8560 Pinout Listing (continued) Signal RIO_RD[0:7] T25, U25, V25, W25, AA25, AB25, AC25, AD25 RIO_RD[0:7] T24, U24, V24, W24, AA24, AB24, AC24, AD24 RIO_RFRAME RIO_RFRAME RIO_TCLK RIO_TCLK RIO_TD[0:7] AE18, AC18, AD19, AE20, AD21, AE22, ...

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Table 54. MPC8560 Pinout Listing (continued) Signal TCK TDI TDO TMS TRST LSSD_MODE L1_TSTCLK L2_TSTCLK TEST_SEL THERM0 THERM1 ASLEEP GND A12, A17, B3, B14, B20, B26, B27, C2, C4, C11,C17, C19, ...

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Package and Pin Listings Table 54. MPC8560 Pinout Listing (continued) Signal REF No Connects OV D1, E4, H3, K4, K10, L7, M5, N3, P22, R19, R25, T2, DD T7, U5, U20, U26, V8, W4, W13, W19, W21, ...

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Table 54. MPC8560 Pinout Listing (continued) Signal PD[4:31] Y1, Y2, Y3, Y4, Y5, Y6, AA8, AA7, AA4, AA3, AA2, AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4, AC3, AC2, Notes: 1.All multiplexed signals are listed only once and do not ...

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Clocking 15 Clocking This section describes the PLL configuration of the MPC8560. Note that the platform clock is identical to the CCB clock. 15.1 Clock Ranges Table 55 provides the clocking specifications for the processor core and specifications for the ...

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Platform/System PLL Ratio The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core complex bus (CCB), and is also called the CCB clock. The values are determined by the ...

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Thermal 15.4 Frequency Options Table 59 shows the expected frequency values for the platform frequency when using a CCB to SYSCLK ratio in comparison to the memory bus speed. Table 59. Frequency Options with Respect to Memory Bus Speeds CCB ...

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Table 60. Package Thermal Characteristics (continued) Characteristic Junction-to-case thermal Notes 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the ...

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Thermal Alpha Novatech 473 Sapena Ct. #15 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI) Loroco Sites 671 East Brokaw Road San Jose, CA 95112 ...

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Conductivity Value Lid (12 × 14 × Lid Adhesive—Collapsed resistance (10 × 12 × 0.050 mm Die (10 × 12 × 0.76 mm) Bump/Underfill—Collapsed resistance (10 ...

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Thermal Figure 53 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. External Resistance Internal Resistance Printed-Circuit Board External Resistance (Note the internal versus external package resistance) Figure 53. Package ...

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Figure 54. Thermal Performance of Select Thermal Interface Materials The system board designer can choose between several types of thermal interface. There are several commercially-available thermal interfaces provided by the following vendors: Chomerics, ...

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Thermal Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 16.2.4 Heat Sink Selection Examples The following section provides a heat sink selection example using one of the commercially available heat sinks. 16.2.4.1 Case 1 For preliminary heat sink ...

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Figure 55. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity 16.2.4.2 Case 2 Every system application has different conditions that the thermal management solution must solve alternate example, ...

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Thermal The spring mounting should be designed to apply the force only directly above the die. By localizing the force, rocking of the heat sink is minimized. One suggested mounting method attaches a plastic fence to the board to provide ...

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Figure 57. Exploded Views ( Heat Sink Attachment using a Plastic Fence The die junction-to-ambient and the heat sink-to-ambient thermal resistances are common figure-of-merits used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise ...

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System Design Information 17 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8560. 17.1 System Clocking The MPC8560 includes three PLLs. 1. The platform PLL generates the platform clock from the externally ...

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Figure 58 shows the PLL power supply filter circuit 17.3 Decoupling Recommendations Due to large address and data buses, and high operating frequencies, the MPC8560 can generate transient power surges and high frequency noise in its power supply, ...

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System Design Information When data is held high, SW1 is closed (SW2 is open) and R OV /2. R then becomes the resistance of the pull-up devices other in value. Then ...

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Configuration Pin Muxing The MPC8560 provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins ...

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System Design Information 17.8 JTAG Configuration Signals Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture. The device requires ...

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COP_SRESET COP_HRESET COP_CHKSTP_OUT 17.8.1 Termination of Unused Signals If the JTAG interface and COP header will not be used, Freescale recommends the following connections: • TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it ...

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System Design Information SRESET From Target Board Sources (if any) HRESET KEY 13 No pin ...

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Document Revision History Table 62 provides a revision history for this hardware specification. Rev. No. 4.2 Added “Note: Rise/Fall Time on CPM Input Pins” and following note text to Specifications.” 4.1 Inserted Figure 3 Added PCI/PCI-X row to Input ...

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Document Revision History Table 62. Document Revision History (continued) Rev. No. 3.2 Updated Table 1 and Added Section 2.1.2, “Power Added CPM port signal drive strength to Updated Table 4 with Maximum power data. Updated Table 4 and Updated Table ...

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Table 62. Document Revision History (continued) Rev. No. 3.0 Table 1—Corrected MII management voltage reference Section 2.1.3—New Table 2—Corrected MII management voltage reference Table 5—Removed ‘minimum’ column Table 5—Added AV Table 8—New Table 9—New Table 9—New Table 13—Added overshoot/undershoot note. ...

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Document Revision History Table 62. Document Revision History (continued) Rev. No. 2.0 Section 1.1—Updated features list to coincide with latest version of the reference manual Table 1 and Table Table 2—Addition of notes 1 and 2 Table 3—Addition of note ...

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Table 62. Document Revision History (continued) Rev. No. 1.2 Section 1.1.1—Updated feature list. Section 1.2.1.1—Updated notes for Table 1. Section 1.2.1.2—Removed 5-V PCI interface overshoot and undershoot figure. Section 1.2.1.3—Added this section to summarize impedance driver settings for various interfaces. ...

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Device Nomenclature 19 Device Nomenclature Ordering information for the parts fully covered by this specification document is provided in Section 19.1, “Part Numbers Fully Addressed by this 19.1 Part Numbers Fully Addressed by this Document Table 63 provides the Freescale ...

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Part Marking Parts are marked as the example shown in Notes Notes : : MMMMM is the 5-digit mask number. MMMMM is the 5-digit mask number. ATWLYYWWA is the traceability code. ATWLYYWWA is the traceability code. CCCCC is the ...

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Device Nomenclature THIS PAGE INTENTIONALLY LEFT BLANK MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 106 Freescale Semiconductor ...

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THIS PAGE INTENTIONALLY LEFT BLANK MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Device Nomenclature 107 ...

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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power ...