mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 22

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

DDR SDRAM
Figure 6
6.2.2.2
Table 18
signals of the DDR controller for various loadings. These numbers are the result of simulations for one
topology. The delay numbers will strongly depend on the topology used. These delay numbers show the
total delay for the address and command to arrive at the DRAM devices. The actual delay could be
different than the delays seen in simulation, depending on the system topology. If a heavily loaded system
is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM.
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MSYNC_OUT
ADDR/CMD
MSYNC_IN
shows the DDR SDRAM output timing diagram.
MDQS[n]
provides approximate delay information that can be expected for the address and command
MDQ[x]
MCK[n]
MCK[n]
Load Effects on Address/Command Bus
4 devices (12 pF)
9 devices (27 pF)
36 devices (108 pF) + 40 pF compensation capacitor
36 devices (108 pF) + 80 pF compensation capacitor
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
t
DDSHMP
Table 18. Expected Delays for Address/Command
t
DDSHMH
t
Figure 6. DDR SDRAM Output Timing Diagram
Write A0
DDKHOV
t
DDKHDX
Load
t
MCK
D0
t
DLL Phase Alignment
MCK
t
NOOP
DDKHOX
t
DDKHDS
D1
t
DDKLDS
t
DDKLDX
t
Delay
MCKH
3.0
3.6
5.0
5.2
t
DDSHME
Unit
ns
ns
ns
ns
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