mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 23

• Manufacturer Part Number: mpc8360e
• Description: Mpc8360e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
MCS(n) output hold with respect to MCK
MCK to MDQS
MDQ/MECC/MDM output setup with respect to MDQS
MDQ/MECC/MDM output hold with respect to MDQS
MDQS preamble start
MDQS epilogue end
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
5. Note that t
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that t
8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
9. In rev2.0 silicon, t
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
Register. For the skew measurements referenced for t
address/command valid with the rising edge of MCK.
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks
by 1/2 applied cycle.
(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t
control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to
the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these
2 parameters have been set to the same adjustment value. See the MPC8360E Integrated Communications Processor
Reference Manual, Rev. 2 for a description and understanding of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.
conventions described in note 1.
-0.9 ns. Please refer to DDR18 in the device errata document.
DDKHAS
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source Synchronous Mode
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
DDKHMH
Parameter
follows the symbol conventions described in note 1. For example, t
maximum meets the specification of 0.6ns. In rev 2.0 silicon, due to errata, t
8
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
DDKLDX
MCK
symbolizes DDR timing (DD) for the time t
(continued)
Symbol
t
t
t
memory clock reference (K) goes from the high (H) state until outputs
AOSKEW
t
t
t
t
t
DDKHDX
DDKHMH
DDKHDS
DDKHMP
DDKHME
DDKHCX
DDKLDS
DDKLDX
,
1
,
it is assumed that the clock adjustment is set to align the
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. Output hold time can be read as DDR timing
-0.5 × t
–0.8
–0.6
Min
2.0
2.7
3.5
0.7
1.0
1.2
0.7
1.0
1.2
MCK
– 0.6
DDKHMH
-0.5 × t
DDKHMH
DDKHMP
Max
MCK
0.7
0.9
MCK
—
—
—
describes the DDR timing
can be modified through
memory clock reference
+ 0.6
follows the symbol
DDR and DDR2 SDRAM
DDKHMH
Unit
ns
ns
ns
ns
ns
ns
minimum is
Notes
5, 9
4
6
6
7
7
for
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