mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 48

• Manufacturer Part Number: mpc8360e
• Description: Mpc8360e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

JTAG
This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the
device.
Table 43
48
At recommended operating conditions (see
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock duty cycle
JTAG external clock rise and fall times
TRST assert time
Input setup times:
Input hold times:
Valid times:
Output hold times:
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications herein follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load
(see
(reference)(state)
t
(V) relative to the t
timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t
going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
JTDVKH
provides the JTAG AC timing specifications as defined in
Figure
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state
21). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
for inputs and t
Table 43. JTAG AC Timing Specifications (Independent of CLKIN)
Parameter
JTG
clock reference (K) going to the high (H) state or setup time. Also, t
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
(first two letters of functional block)(reference)(state)(signal)(state)
Table
2).
TMS, TDI
TMS, TDI
TDO
TDO
TDO
TCLK
TCLK
.
.
t
t
JTGR
JTKHKL
Symbol
t
t
t
t
t
t
t
t
t
t
JTDVKH
JTDXKH
JTKLOV
JTKLDX
JTKLOZ
JTKLDV
JTKLOX
JTKLDZ
JTIVKH
JTIXKH
t
TRST
f
t
JTG
JTG
& t
/t
JTGF
JTG
2
(first two letters of functional block)(signal)(state)
Min
30
45
25
10
10
0
0
4
4
2
2
2
2
2
2
Figure 29
TCLK
for outputs. For example,
Max
33.3
to the midpoint of the signal
55
11
11
19
—
—
—
—
—
—
—
—
2
9
through
JTDXKH
JTG
clock reference (K)
Freescale Semiconductor
1
symbolizes JTAG
MHz
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
%
32.
Notes
5, 6
3
4
4
5
5
6