spc560p50l3 STMicroelectronics, spc560p50l3 Datasheet - Page 18

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spc560p50l3

Manufacturer Part Number
spc560p50l3
Description
32-bit Power Architecture? Based Mcu For Chassis & Safety Applications
Manufacturer
STMicroelectronics
Datasheet

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Overview of the SPC560Px
3.2.19
18/31
The FlexCAN module provides the following features:
Safety port (FlexCAN)
The SPC560Px MCU has a second CAN controller synthesized to run at high bit rates to be
used as a safety port. The CAN module of the safety port provides the following features:
Full implementation of the CAN protocol specification, Version 2.0B
32 message buffers of zero to eight bytes data length
Each message buffer configurable as Rx or Tx, all supporting standard and extended
messages
Programmable loop-back mode supporting self-test operation
Three programmable mask registers
Programmable transmit-first scheme: lowest ID or lowest buffer number
Time stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Transmit features
Receive features
Programmable clock source
Identical to the FlexCAN module
Bit rate up to 7.5 Mbit/s at 60 MHz CPU clock using direct connection between CAN
modules (no physical transceiver required)
32 message buffers of zero to eight bytes data length
Can be used as a second independent CAN module
Standard data and remote frames
Extended data and remote frames
Zero to eight bytes data length
Programmable bit rate up to 1 Mbit/s
Supports configuration of multiple mailboxes to form message queues of scalable
depth
Arbitration scheme according to message ID or message buffer number
Internal arbitration to guarantee no inner or outer priority inversion
Transmit abort procedure and notification
Individual programmable filters for each mailbox
Eight mailboxes configurable as a six-entry receive FIFO
Eight programmable acceptance filters for receive FIFO
System clock
Direct oscillator clock to avoid PLL jitter
Doc ID 13950 Rev 5
SPC560P44Lx, SPC560P50Lx

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