at75c220 ATMEL Corporation, at75c220 Datasheet - Page 100

• Manufacturer Part Number: at75c220
• Description: Smart Internet Appliance Processor Siap
• Manufacturer: ATMEL Corporation

Signal Name Description
Note:
Timer/Counter Description
The three timer/counter channels are independent and
identical in operation. The registers for channel program-
ming are listed in Table 25 on page 106.
Counter
Each timer/counter channel is organized around a 16-bit
counter. The value of the counter is incremented at each
positive edge of the selected clock. When the counter has
reached the value 0xFFFF and passes to 0x0000, an over-
flow occurs and the bit COVFS in TC_SR (Status Register)
is set.
The current value of the counter is accessible in real time
by reading TC_CV. The counter can be reset by a trigger.
In this case, the counter value passes to 0x0000 on the
next valid edge of the selected clock.
Clock Selection
At block level, input clock signals of each channel can
either be connected to the external inputs TCLK0, TCLK1
100
Channel Signal
XC0, XC1, XC2
TIOA
TIOB
INT
SYNC
Block Signal
TCLK0, TCLK1, TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
After a hardware reset, the timer/counter block pins are controlled by the PIO controller. They must be configured to be con-
trolled by the peripheral before being used.
AT75C220
Description
External clock inputs
Capture mode: General-purpose input
Waveform mode: General-purpose output
Capture mode: General-purpose input
Waveform mode: General-purpose input/output
Interrupt signal output
Synchronization input signal
External clock inputs
TIOA signal for Channel 0
TIOB signal for Channel 0
TIOA signal for Channel 1
TIOB signal for Channel 1
TIOA signal for Channel 2
TIOB signal for Channel 2
or TCLK2, or be connected to the configurable I/O signals
TIOA0, TIOA1 or TIOA2 for chaining by programming the
TC_BMR (Block Mode).
Each channel can independently select an internal or exter-
nal clock source for its counter:
•
•
The selected clock can be inverted with the CLKI bit in
TC_CMR (Channel Mode). This allows counting on the
opposite edges of the clock.
The burst function allows the clock to be validated when an
external signal is high. The BURST parameter in the Mode
Register defines this signal (none, XC0, XC1, XC2).
Note:
Internal clock signals: ACLK/2, ACLK/8, ACLK/32,
ACLK/128, ACLK/1024
External clock signals: XC0, XC1 or XC2
In all cases, if an external clock is used, the duration of
each of its levels must be longer than the system clock
(ACLK) period. The external clock frequency must be at
least 2.5 times lower than the system clock (ACLK).
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I