at75c220 ATMEL Corporation, at75c220 Datasheet - Page 101

• Manufacturer Part Number: at75c220
• Description: Smart Internet Appliance Processor Siap
• Manufacturer: ATMEL Corporation

Figure 23. Clock Selection
Clock Control
The clock of each counter can be controlled in two different
ways: it can be enabled/disabled and started/stopped.
1. The clock can be enabled or disabled by the user
2. The clock can also be started or stopped: a trigger
Timer/Counter Operating Modes
Each timer/counter channel can independently operate in
two different modes:
1. Capture mode allows measurement on signals
2. Waveform mode allows wave generation
The timer/counter operating mode is programmed with the
WAVE bit in the TC Mode Register. In capture mode, TIOA
and TIOB are configured as inputs. In waveform mode,
TIOA is always configured to be an output and TIOB is an
output if it is not selected to be the external trigger.
with the CLKEN and the CLKDIS commands in the
Control Register. In capture mode it can be disabled
by an RB load event if LDBDIS is set to 1 in
TC_CMR. In waveform mode it can be disabled by
an RC Compare event if CPCDIS is set to 1 in
TC_CMR. When disabled, the start or the stop
actions have no effect: only a CLKEN command in
the Control Register can re-enable the clock. When
the clock is enabled, the CLKSTA bit is set in the
Status Register.
(software, synchro, external or compare) always
starts the clock. The clock can be stopped by an RB
load event in capture mode (LDBSTOP = 1 in
TC_CMR) or a RC compare event in waveform
mode (CPCSTOP = 1 in TC_CMR). The start and
the stop commands have an effect only if the clock
is enabled.
ACLK/2
ACLK/8
ACLK/32
ACLK/128
ACLK/1024
XC0
XC1
XC2
1
CLKS
BURST
CLKI
Selected
Clock
Figure 24. Clock Control
Trigger
A trigger resets the counter and starts the counter clock.
Three types of triggers are common to both modes, and a
fourth external trigger is available to each mode.
The following triggers are common to both modes:
1. Software trigger: Each channel has a software trig-
2. SYNC: Each channel has a synchronization signal,
3. Compare RC trigger: RC is implemented in each
The timer/counter channel can also be configured to have
an external trigger. In capture mode, the external trigger
signal can be selected between TIOA and TIOB. In wave-
form mode, an external event can be programmed on one
of the following signals: TIOB, XC0, XC1 or XC2. This
external event can then be programmed to perform a trig-
ger by setting ENETRG in TC_CMR.
If an external trigger is used, the duration of the pulses
must be longer than the system clock (ACLK) period in
order to be detected.
Whatever the trigger used, it will be taken into account at
the following active edge of the selected clock. This means
that the counter value may not read zero just after a trigger,
especially when a low-frequency signal is selected as the
clock.
Selected
Counter
Clock
Clock
ger, available by setting SWTRG in TC_CCR.
SYNC. When asserted, this signal has the same
effect as a software trigger. The SYNC signals of all
channels are asserted simultaneously by writing
TC_BCR (Block Control) with SYNC set.
channel and can provide a trigger when the counter
value matches the RC value if CPCTRG is set in
TC_CMR.
Q
S
R
Trigger
CLKSTA
Q
CLKEN
R
S
Event
Stop
CLKDIS
Disable
Event
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