adau1373 Analog Devices, Inc., adau1373 Datasheet - Page 76

• Manufacturer Part Number: adau1373
• Description: Low Power Codec With Speaker And Headphone Amplifier Adau1373
• Manufacturer: Analog Devices, Inc.

ADAU1373
Reg Name
AA DRC3_CTRL11
AB DRC3_CTRL12
AC DRC3_CTRL13
AD DRC3_CTRL14
AE DRC3_CTRL15
AF DRC3_CTRL16
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA PRE_HPF4_
BB PRE_HPF5_
BC PRE_HPF5_
BD PRE_HPF_
BE
BF
C0 E3D_CTRL1
C1 E3D_CTRL2
C2 ALC_CTRL0
C3 ALC_CTRL1
C4 ALC_CTRL2
C5 ALC_CTRL3
C6 ALC_CTRL4
C7 ALC_CTRL5
C8 ALC_CTRL6
DC FDSP_SEL1
DD FDSP_SEL2
DE FDSP_SEL3
DF FDSP_SEL4
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA PAD_CTRL2
EB
EC LPCNTCTRL
ED CHIP_ID_HI
EE
EF
FF
MDRC_PRE_
FILTER
MDRC_SPL_
CTRL
MDRC_CTRL
PRE_HPF1_
COEFH
PRE_HPF1_
COEFL
PRE_HPF2_
COEFH
PRE_HPF2_
COEFL
PRE_HPF3_
COEFH
PRE_HPF3_
COEFL
PRE_HPF4_
COEFH
COEFL
COEFH
COEFL
CTRL
EQ_CTRL1
EQ_CTRL2
PBALPCTRL1
PBBLPCTRL2
DIGMICCTRL
GPIOSEL1
GPIOSEL2
IRQ_MASK
IRQ_RAW
IRQ_STATE
IRQEN
PAD_CTRL1
DIGEN
CHIP_ID_MID
CHIP_ID_LO
SOFT_RESET
Bits
[7:0]
[7:0]
[7:0]
[7:0] DRCNGTGT
[7:0] RESERVED
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0] EQEN
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0] HLDRST
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0] PBALPANA
[7:0] PBBLPANA
[7:0] MICLRMODE
[7:0]
[7:0]
[7:0] ASRCC_IRQ_
[7:0] ASRCC_IRQ_
[7:0] ASRCC_IRQ_
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit 7
MASK
RAW_STATE
STATUS
RESERVED
RESERVED
RESERVED
Bit 6
DRCNGHDEN
EQBP7
ALCHPF
ASRCB_IRQ_
MASK
ASRCB_IRQ_
RAW_STATE
ASRCB_IRQ_
STATUS
RESERVED
RESERVED
RESERVED
MDRC_CROSS_HIGH
DRCHTNOR
LPC_B_CNT
E3D_LEVEL
ALCNGATT
DRCGSATT
RESERVED
RESERVED
ALCNGTH
GPIO2SEL
GPIO4SEL
ALCTAV
ALCATT
ALCLVL
ALCRIP
Bit 5
DRCNGSRC
EQBP6
ASRCA_IRQ_
MASK
ASRCA_IRQ_
RAW_STATE
ASRCA_IRQ_
STATUS
I2CFILTER_
BYPASS
DMICPOLSWAP
BASS_EN_SEL
DRC3_SEL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
E3D_SEL
EQ_SEL
NGMODE
PBALPWL
PBBLPWL
Rev. 0 | Page 76 of 296
Bit 4
DRCCESRC
PRE_HPF5_EN
EQ_UPDING
EQBP5
DRC_IRQ_
MASK
DRC_IRQ_
RAW_STATE
DRC_IRQ_
STATUS
I2CDRV
FDSPEN
SIG_DET_RMS
RESERVED
PRE_HPF1_COEFH
PRE_HPF2_COEFH
PRE_HPF3_COEFH
PRE_HPF4_COEFH
PRE_HPF5_COEFH
CHIP_ID_LOW
CHIP_ID_MID
MDRC_HPF
CHIP_ID_HI
SOFT_RST
DRCG
Bit 3
DRCLMSRC
PRE_HPF4_EN
EQ_UPD_CLR
EQBP4
RESERVED
RESERVED
RESERVED
ALC_4CHEN
DMICBLRSWAP
PLL_UNLOCK_
MASK
PLL_UNLOCK_
RAW_STATE
PLL_UNLOCK_
STATUS
DMICCLKDRV
GPIO4DRV
DRECEN
ALCEN
Bit 2
DRCNGEN
ALG_NGEN
MDRC_LPFEN
PRE_HPF3_EN
EQ_FORMAT
EQBP3
DIGMICBEN
HP_CFG_MASK
HP_CFG_
RAW_STATE
HP_CFG_
STATUS
CDRV
GPIO3DRV
RECEN
E3D_GAIN
MDRC_CROSS_LOW
E3D_ALPHA
LPC_A_CNT
ALCNGHLD
PBALPMODE
PBBLPMODE
DRCGSDEC
ALCNGREC
DRCHTNG
GPIO1SEL
GPIO3SEL
ALCMAX
ALCHLD
ALCREC
ALCREF
PRE_HPF2_COEFL
PRE_HPF3_COEFL
PRE_HPF4_COEFL
PRE_HPF5_COEFL
PRE_HPF_COEFL
Bit 1
DRCIRQ_MODE
MDRC_HPFEN
PRE_HPF2_EN
EQ_UPD
EQBP2
DMICALRSWAP
HP_DECT_MASK AFAULT_MASK
HP_DECT_
RAW_STATE
HP_DECT_
STATUS
BDRV
GPIO2DRV
PBBEN
DRC2_SEL
DRC1_SEL
HPF_SEL
ALC_SEL
SIG_DET_PK
MDRC_LPF
RESERVED
ALCMODE
DRCEN
Bit 0
DRCIRQ_EN
MDRC_EN
PRE_HPF1_EN
EQ_WR_EN
EQBP1
E3D_EN
PBALPEN
PBBLPEN
DIGMICAEN
AFAULT_
RAW_STATE
AFAULT_STATUS 0x00
IRQEN
ADRV
GPIO1DRV
PBAEN
Reset RW
0x88
0x7A RW
0xDF RW
0x20
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x1F
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
02
0x00
1F
0F
0x00
0x00
13
73
0B
0x00
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
RW
RW
RW
RW
RW
R
R
R
MMRW