sc18is602 NXP Semiconductors, sc18is602 Datasheet - Page 8

• Manufacturer Part Number: sc18is602
• Description: Sc18is602/sc18is603 I?c-bus To Spi Bridge
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC18IS602_603_3
Product data sheet
7.1.6 Clear Interrupt - Function ID F1h
7.1.7 Idle mode - Function ID F2h
7.1.8 GPIO Write - Function ID F4h
An interrupt is generated by the SC18IS602/603 after any SPI transmission has been
completed. This interrupt can be cleared (INT pin HIGH) by sending a ‘Clear Interrupt’
command. It is not necessary to clear the interrupt; when polling the device, this function
may be ignored.
A low-power mode may be entered by sending the ‘Idle Mode’ command.
The Idle mode will be exited when its I
The state of the pins defined as GPIO may be changed using the Port Write function.
The data byte following the F4h command will determine the state of SS3, SS2, SS1, and
SS0, if they are configured as GPIO. The Port Enable function will define if these pins are
used as SPI Slave Selects or if they are GPIO.
Table 6.
[1]
Bit
Symbol
Reset
Fig 11. Clear Interrupt
Fig 12. Idle mode
Fig 13. GPIO Write
SS3 does not exist in the SC18IS603.
GPIO Write (F0h) bit allocation
X
X
7
S
SLAVE ADDRESS
Rev. 03 — 13 August 2007
6
X
X
S
S
SLAVE ADDRESS
SLAVE ADDRESS
X
X
5
W
2
C-bus address is detected.
A
W
W
4
X
X
F4h
A
A
SS3
F1h
F2h
A
3
0
[1]
SC18IS602/603
002aac452
002aac453
DATA
A
A
SS2
P
P
2
0
002aac454
I
2
A
C-bus to SPI bridge
P
© NXP B.V. 2007. All rights reserved.
SS1
1
0
SS0
0
0
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