isp1160 NXP Semiconductors, isp1160 Datasheet - Page 44

• Manufacturer Part Number: isp1160
• Description: Isp1160 Embedded Universal Serial Bus Host Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 20:
9397 750 13963
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmInterval register: bit allocation
reserved
R/W
R/W
FIT
31
7
0
0
10.2.1 HcFmInterval register (R/W: 0DH/8DH)
10.2 HC frame counter registers
Table 19:
The HcFmInterval register contains a 14-bit value which indicates the bit time interval
in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the
full-speed maximum packet size that the HC may transmit or receive without causing
a scheduling overrun. The HCD may carry out minor adjustments on the
FrameInterval by writing a new value at each SOF. This allows the HC to synchronize
with an external clock resource and to adjust any unknown clock offset.
Code (Hex): 0D — read
Code (Hex): 8D — write
Bit
31
30 to 7
6
5
4
3
2
1
0
RHSC
R/W
R/W
30
6
0
0
HcInterruptDisable register: bit description
Symbol
MIE
-
RHSC
FNO
UE
RD
SF
-
SO
FNO
R/W
R/W
29
5
0
0
Rev. 05 — 24 December 2004
Description
A logic 0 is ignored by the HC. A logic 1 disables interrupt
generation due to events specified in other bits of this register. This
field is set after a hardware or software reset.
reserved
0 — ignore
1 — disable interrupt generation due to Root Hub Status Change
0 — ignore
1 — disable interrupt generation due to Frame Number Overflow
0 — ignore
1 — disable interrupt generation due to Unrecoverable Error
0 — ignore
1 — disable interrupt generation due to Resume Detect
0 — ignore
1 — disable interrupt generation due to Start of Frame
reserved
0 — ignore
1 — disable interrupt generation due to Scheduling Overrun
R/W
R/W
UE
28
4
0
0
FSMPS[14:8]
R/W
R/W
RD
27
3
0
0
Embedded USB Host Controller
R/W
R/W
SF
26
2
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
reserved
R/W
R/W
25
1
0
0
ISP1160
R/W
R/W
SO
24
0
0
0
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