isp1181 NXP Semiconductors, isp1181 Datasheet - Page 34

no-image

isp1181

Manufacturer Part Number
isp1181
Description
Isp1181 Full-speed Universal Serial Bus Interface Device
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
isp1181ABS
Manufacturer:
PHILIPS
Quantity:
57 426
Part Number:
isp1181ABS
Manufacturer:
HARRIS
Quantity:
710
Part Number:
isp1181ABS
Manufacturer:
PHI/PB
Quantity:
1
Part Number:
isp1181ABS
Manufacturer:
ST
0
Part Number:
isp1181ABS
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Part Number:
isp1181ADGG
Manufacturer:
EBM
Quantity:
2 000
Part Number:
isp1181ADGG
Manufacturer:
ST
0
Part Number:
isp1181ADGG
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
isp1181ADGGTM
Manufacturer:
ST
0
Part Number:
isp1181BBS
Manufacturer:
PHI/Pb
Quantity:
810
Part Number:
isp1181BBS
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
isp1181BD
Manufacturer:
NXPLIPS
Quantity:
5 510
Part Number:
isp1181BD
Manufacturer:
SAMSUNS
Quantity:
5 510
Part Number:
isp1181BDGG
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Philips Semiconductors
9397 750 08938
Product data
12.2.2 Read Endpoint Status
Table 29:
Table 30:
Table 31:
Remark: There is no protection against writing or reading past a buffer’s boundary,
against writing into an OUT buffer or reading from an IN buffer. Any of these actions
could cause an incorrect operation. Data residing in an OUT buffer are only
meaningful after a successful transaction. Exception: during DMA access of a
double-buffered endpoint, the buffer pointer automatically points to the secondary
buffer after reaching the end of the primary buffer.
This command is used to read the status of an endpoint FIFO. The command
accesses the Endpoint Status Register, the bit allocation of which is shown in
Table
corresponding endpoint in the Interrupt Register (see
All bits of the Endpoint Status Register are read-only. Bit EPSTAL is controlled by the
Stall/Unstall commands and by the reception of a SETUP token (see
Code (Hex): 50 to 5F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 byte
Byte #
(8-bit bus)
3
(N
A0
1
0
0
0
0
0
0
A0
1
0
0
0
1)
32. Reading the Endpoint Status Register will clear the interrupt bit set for the
Phase
command
data
data
data
data
data
data
Phase
command
data
data
data
Endpoint FIFO organization
Example of endpoint FIFO access (8-bit bus width)
Example of endpoint FIFO access (16-bit bus width)
Word #
(16-bit bus)
1 (upper byte)
M = (N + 1) DIV 2
Rev. 04 — 30 October 2001
Bus lines
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
Bus lines
D[7:0]
D[15:8]
D[15:0]
D[15:0]
D[15:0]
Byte #
-
0
1
2
3
4
5
Word #
-
-
0
1
2
…continued
Description
data byte 2
data byte N
Description
command code (00H to 1FH)
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
data byte 3
data byte 4
Description
command code (00H to 1FH)
ignored
packet length
data word 1 (data byte 2, data byte 1)
data word 2 (data byte 4, data byte 3)
Table
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Full-speed USB interface
48).
ISP1181
Section
12.2.3).
34 of 71

Related parts for isp1181