isp1507fbs NXP Semiconductors, isp1507fbs Datasheet - Page 35

• Manufacturer Part Number: isp1507fbs
• Description: Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1507E_ISP1507F_1
Product data sheet
Fig 14. High-speed receive-to-transmit packet timing
CLOCK
DP or
DATA
[3:0]
STP
NXT
DIR
DM
D
N 4
DATA
D
N 3
9.9 Preamble
D
EOP
N 2
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the FUNC_CTRL register (see
preamble mode, the ISP1507 operates just as in full-speed mode, and sends all data with
the full-speed rise time and fall time. Whenever the link transmits a USB packet in
preamble mode, the ISP1507 will automatically send a preamble header at full-speed bit
rate before sending the link packet at low-speed bit rate. The ISP1507 will ensure a
minimum gap of four full-speed bit times between the last bit of the full-speed PRE PID
and the first bit of the low-speed packet SYNC. The ISP1507 will drive a J for at least one
full-speed bit time after sending the PRE PID, after which the pull-up resistor can hold the
J state on the bus. An example transmit packet is shown in
In preamble mode, the ISP1507 can also receive low-speed packets from the full-speed
bus.
(three to eight clocks)
D
N 1
RX end delay
D
N
turnaround
USB interpacket delay (8 to 192 high-speed bit times)
Rev. 01 — 28 May 2008
link decision time (1 to 14 clocks)
IDLE
ISP1507E; ISP1507F
ULPI HS USB OTG transceiver
Figure
Section
15.
10.1.2). When in
(one to two clocks)
TXCMD
TX start delay
© NXP B.V. 2008. All rights reserved.
SYNC
D0
004aaa892
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D1