isp1505a NXP Semiconductors, isp1505a Datasheet
isp1505a
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isp1505a Summary of contents
Page 1
... ISP1505A; ISP1505C ULPI Hi-Speed Universal Serial Bus host and peripheral transceiver Rev. 01 — 19 October 2006 1. General description The ISP1505 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and UTMI+ Low Pin Interface (ULPI) Specifi ...
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... MHz, 8-bit interface between the core and the transceiver N Supports both 60 MHz input clock and 60 MHz output clock configurations N Integrated Phase-Locked Loop (PLL) with auto-configuring support for 60 MHz input clock, or one crystal or clock frequency: 19.2 MHz (ISP1505ABS), 26 MHz (ISP1505CBS) N Fully programmable ULPI-compliant register set N ...
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... MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Package Name Description HVQFN24 plastic thermal enhanced very thin quad flat package; ...
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... EXTERNAL BUS GLOBAL POWER-ON RESET RESET PLL GLOBAL CLOCKS CRYSTAL OSCILLATOR ISP1505 interface voltage internal power V REF VOLTAGE REGULATOR Rev. 01 — 19 October 2006 ISP1505A; ISP1505C 6 DP HIGH-SPEED USB ATX TERMINATION 5 DM RESISTORS V BUS COMPARATORS BUS FAULT SRP CHARGE AND DISCHARGE ...
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... FAULT (input) — Input pin for the external V signal. If this pin is not used as either tolerant 3.3 V regulator output crystal oscillator or clock input crystal oscillator output Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 18 DATA6 17 DATA7 16 NXT ISP1505 ...
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... PCB ground Section 7.10. Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver power switch or external charge BUS . CC(I/O) Section 16 ...
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... Squelch circuit to detect high-speed bus activity ISP1505A_ISP1505C_1 Product data sheet source control BUS monitoring, charging and discharging Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Section 9. © NXP B.V. 2006. All rights reserved ...
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... During power-up expected that the comparator output will be ignored. ISP1505A_ISP1505C_1 Product data sheet high-speed bus terminations on DP and DM for peripheral and host modes Section 16. . Any voltage on V A_VBUS_VLD Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Table 7. CC < 3 valid comparator, session valid BUS voltage level ...
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... The data bus can be reconfigured to carry various data types, as given in Section ISP1505A_ISP1505C_1 Product data sheet . hys(B_SESS_VLD) power. First, the B-device makes sure that V Section 9. Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver is below the B-device BUS . B_SESS_END is fully discharged from the BUS by setting the CHRG_VBUS BUS ...
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... VBUS overcurrent or fault circuit is used, the output fault indicator of that BUS fault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the link Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Section power must be provided CC(I/O) power input is delayed with respect to ...
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... Product data sheet ULPI HS USB host and peripheral transceiver Section 16. . CC(I/O) Section 9.3.2. switch or charge pump enable circuit to control the external V BUS pullup Section 16. Rev. 01 — 19 October 2006 ISP1505A; ISP1505C Section 16. . CC(I/ required when PSW_N is used. This © NXP B.V. 2006. All rights reserved. BUS ...
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... Product data sheet ULPI HS USB host and peripheral transceiver BUS state in RXCMD is not 11b), it must disable the external BUS 9.3.1. Rev. 01 — 19 October 2006 ISP1505A; ISP1505C power source by setting the BUS power source. If the link detects an © NXP B.V. 2006. All rights reserved ...
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... This acts as a ground to all circuits in the ISP1505. To ensure correct operation of the ISP1505, GND must be soldered to the cleanest ground available. ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 01 — 19 October 2006 © NXP B.V. 2006. All rights reserved. ...
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... DIR changes value. This is called the turnaround cycle. Data lines have fixed direction and different meaning in low-power and serial modes. Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 15. A description of the ULPI pin behavior in Section 9. ...
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... NXT is not used in low-power or serial mode. Description combinatorial LINESTATE0 directly driven by analog receiver combinatorial LINESTATE1 directly driven by analog receiver Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver supply (see Table CC 41). ...
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... O reserved; the ISP1505 will drive this pin to LOW Table Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 5. To enter 6-pin serial mode, the link sets 6. To enter 3-pin serial mode, the link sets the © NXP B.V. 2006. All rights reserved. ...
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... Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 7. Resistor setting signals are defined as follows: Internal resistor settings DM_PULL RPU_ RPD_ DOWN DP_EN DP_EN ...
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... Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Internal resistor settings DM_PULL RPU_ RPD_ DOWN DP_EN DP_EN ...
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... POR(trip) w(REG1V8_L PORP shows a typical start-up sequence. Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver , for at least POR(trip) , and then rises above V POR(trip Figure 3 shows a possible curve of REG1V8. The , another POR pulse is ...
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... The ULPI interface is ready for use. ISP1505A_ISP1505C_1 Product data sheet Figure crystal is attached and a 60 MHz clock is driven into the CLOCK Figure 4. Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver © NXP B.V. 2006. All rights reserved ...
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... If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL startup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver D internal reset power ...
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... PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG Control register to logic 1. When the DRV_VBUS_EXT bit is set, the DRV_VBUS bit can be set to any value and will be ignored. ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Hi-Z (link must drive) Hi-Z (input) Hi-Z (link must drive) ...
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... NOOP 00 0000b NOPID 00 XXXXb PID Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver fault detector circuits. An overcurrent detection pin on the ISP1505 and the link can BUS fault detector circuits that output a digital fault /FAULT pin. To enable ...
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... A_VBUS_VLD RxActive Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Command description Extended register write command (optional). The 8-bit address must be provided after the command is accepted. Register write command with 6-bit immediate address. Extended register read command (optional). The 8-bit address must be provided after the command is accepted ...
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... HS_Differential_Receiver_Output invalid !squelch and !HS_Differential_Receiver_Output invalid invalid Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Back-to-back RXCMDs turnaround RXCMD RXCMD © NXP B.V. 2006. All rights reserved. turnaround 004aaa695 ...
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... FAULT share the same pin and cannot be simultaneously used. BUS state encoding”. BUS A_VBUS_VLD comparator (V < 4.4 V) BUS internal A_VBUS_VLD complement output Rev. 01 — 19 October 2006 ISP1505A; ISP1505C Chirp squelch !squelch and HS_Differential_Receiver_Output !squelch and !HS_Differential_Receiver_Output invalid state are directly BUS Figure state encoding is given in Section “ ...
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... SESS_END must be used to detect BUS has dropped to a LOW level, allowing the B-device to safely initiate V BUS Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver The V state encoding is shown in BUS and take appropriate action. ...
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... When the ISP1505 has detected an error while receiving a USB packet, it HostDisconnect is encoded into the RxEvent field of the RXCMD. shows register read and write sequences. The ISP1505 supports immediate Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Section 9.8.1. ...
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... USB reset and high-speed detection Table 11 the peripheral is in low-power mode, it must wake 0 Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver TXCMD D (EXTW extended register read ...
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... USB packets. For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 01 — 19 October 2006 © NXP B.V. 2006. All rights reserved ...
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... K (10b) (00b) TXCMD NOPID K K ... (HS) 10 (chirp) squelch peripheral chirp K (10b) (00b) Rev. 01 — 19 October 2006 ISP1505A; ISP1505C host chirp TXCMD (REGW) NOPID K J ... K J host chirp K (10b) or chirp J (01b) RXCMDs TXCMD (REGW ...
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... Table 14 for correct USB system operation. Examples of high-speed Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Figure 10. For details on USB ISP1505 ISP1505 ISP1505 asserts DIR, sends sends ...
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... Any subsequent transmission can occur after this time. USB interpacket delay (88 to 192 high-speed bit times) EOP link decision time ( clocks) Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver IDLE (one to two clocks) © NXP B.V. 2006. All rights reserved. ...
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... USB interpacket delay (8 to 192 high-speed bit times) IDLE N turnaround link decision time ( clocks) Figure 13. Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver TXCMD TX start delay (one to two clocks) © NXP B.V. 2006. All rights reserved. SYNC D0 ...
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... PRE ID DP and DM timing is not to scale. illustrates how a host or a hub places a full-speed or low-speed peripheral into Figure 14 timing is not to scale, and does not show all RXCMD Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver D1 D0 IDLE (min LS D0 ...
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... Product data sheet SUSPEND RESUME K TXCMD TXCMD (REGW) NOPID LINESTATE J LINE STATE K 00b J illustrates how a host or a hub places a high-speed enabled peripheral into Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver EOP K ... K TXCMD K 10b K SE0 J SE0 ...
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... The peripheral link sees terminations (TERMSELECT is set to 0b). The host link sets Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver terminations, and enables the 1.5 k terminations (TERMSELECT is set to © NXP B.V. 2006. All rights reserved. ...
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... Product data sheet FS SUSPEND TXCMD TXCMD (REGW) NOPID 01b 00b FS J (01b) LINESTATE K LINESTATE J 01b 00b FS J (01b) Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver RESUME K HS IDLE TXCMD ... (REGW) 00b 10b 00b FS K (10b) SQUELCH (00b) ...
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... SE0 of the EOP is completed. This can be achieved by writing XCVRSELECT = 00b and TERMSELECT = 0b after LINESTATE indicates SE0. ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 01 — 19 October 2006 © NXP B.V. 2006. All rights reserved ...
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... EOP when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver TXCMD TXCMD ...
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... The following subsections describe how to use the ISP1505 OTG components. ISP1505A_ISP1505C_1 Product data sheet ULPI HS USB host and peripheral transceiver 00h 00h 80h PID 00h SYNC PID BUS Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ... ... D FEh N DATA PAYLOAD EOP IDLE 004aaa719 ...
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... B-device to discharge V DN(VBUS) BUS is below V BUS B_SESS_END and Figure 19 provide examples of 6-pin serial mode and 3-pin serial mode, Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver , V A_VBUS_VLD A_SESS_VLD and V are combined into B_SESS_VLD Section 7.6. Changes in comparator values Section 9 ...
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... DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 19. Example of transmit followed by receive in 3-bit serial mode ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver TRANSMIT DATA EOP TRANSMIT DATA SYNC EOP Rev. 01 — 19 October 2006 RECEIVE SYNC ...
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... DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle, avoiding data bus contention. ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 01 — 19 October 2006 © NXP B.V. 2006. All rights reserved ...
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... FFh shows the bit description of the register. Description CCh Vendor ID Low: Lower byte of the NXP vendor ID supplied by USB-IF; has a fixed value of CCh Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver References [3] [ Section 10.1.1 on page 45 ...
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... Description 15h Product ID High: Upper byte of the NXP product ID number; has a fixed value of 15h Table 20 RESET OPMODE[1: R/W/S/C R/W/S/C Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Table 17. Table 18. Table 19 TERM XCVRSELECT[1:0] SELECT ...
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... Access R/W/S/C R/W/S/C ISP1505A_ISP1505C_1 Product data sheet 7. Table IND_ reserved COMPL R/W/S/C R/W/S/C Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver provides the bit allocation of the register CLOCK_ reserved 3PIN_ SUSPENDM FSLS_ SERIAL 0 0 R/W/S/C R/W/S/C R/W/S 6PIN_ FSLS_ ...
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... Table 24 DRV_ CHRG_ VBUS VBUS R/W/S/C R/W/S/C Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver comparator. Either a digital FAULT is input on the /FAULT pin, not both. This bit BUS Section 9.5.2. DISCHRG_ DM_PULL DP_PULL VBUS DOWN DOWN ...
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... Table 26 shows the bit allocation of the register reserved R/W/S/C R/W/S/C Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver overcurrent indicator. BUS supply through the RESET_N/PSW_N pin. BUS . BUS . BUS . If DRV_VBUS_EXT is set to logic 1, BUS pulsing SRP. The link must ...
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... Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on Table 30) indicates the current value of the interrupt source signal reserved Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver SESS_ SESS_ VBUS_ END_F VALID_F VALID_F ...
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... Host Disconnect Latch: Automatically set when an unmasked event occurs on HOST_DISCON. Cleared when this register is read reserved Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver valid voltage comparator. BUS Table 32 SESS_ SESS_ VBUS_ END_L ...
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... PHY will not be affected. provides the bit allocation of the Power Control register reserved R/W/S/C R/W/S/C Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver BVALID_ BVALID_ reserved FALL RISE ...
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... Addresses 40h to FFh are not implemented. Operating on these addresses will have no effect on the PHY. ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 01 — 19 October 2006 © NXP B.V. 2006. All rights reserved ...
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... GND to achieve this 4 kV ESD protection (see BUS 1500 charge current discharge limit resistor resistance storage C S capacitor 100 pF Rev. 01 — 19 October 2006 ISP1505A; ISP1505C and GND) have a BUS Figure , see Section VBUS DEVICE UNDER TEST A B 0.1 F © NXP B.V. 2006. All rights reserved. 20). 16. ...
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... DP, DM, V and GND; BUS I < all other pins; I < Conditions on pins CLOCK, STP, DATA[7:0] and RESET_N/PSW_N on pin V /FAULT BUS on pins DP and DM on pin XTAL1 . CC Rev. 01 — 19 October 2006 ISP1505A; ISP1505C Min Max 0.5 +4.6 0.5 +4 CC(I/O) 0.5 +6.0 0.5 +2.5 [ 100 ...
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... C; unless otherwise specified. CC(I/O) amb Conditions CC(I/ 0 CC(I/ 0 < V < CC(I/O) Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ 3.0 3.3 1.65 1.8 1 215 - [ [ [ [ ...
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... C; unless otherwise specified. CC(I/O) amb Conditions includes V range DI pull-up on pin pull-down on pins DP and DM GND L Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ Max 3.5 Min Typ Max ...
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... C to +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. CC(I/O) amb Conditions for 1.5 k pull-up resistor includes V range DI pin to GND steady-state drive Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ 3.0 - 1425 1500 100 - 525 - 300 - ...
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... CHRG_VBUS is logic 1 connect to GND when DISCHRG_VBUS is logic +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. CC(I/O) amb Conditions SUSPENDM is logic 1 Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ Max 4.4 4.5 4.65 0.8 1.6 2.0 70 140 200 0 ...
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... XTAL1 measured from power good or assertion of pin STP Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ 0 ...
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... Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ Max 5 ...
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... 200 pF to 600 pF; L 1.5 k pull- enabled excluding the first LR LF transition from the idle state Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ Max 3.4 3 7.7 4.1 - 3.1 2 7.3 3 ...
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... Figure 24 DP RX_RCV, RX_DP and RX_DM; see Figure 24 DP RX_RCV, RX_DP and RX_DM; see Figure 24 DP RX_RCV, RX_DP and RX_DM; see Figure 24 Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ Max - - ...
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... Fig 24. Timing of DP and DM to RX_RCV, RX_DP and CLOCK t t su(STP) h(STP) (STP su(DATA) h(DATA) (8-BIT) (8-BIT) Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 0 PLH(drv) differential V CRS data lines 2 CRS 0 PLH(rcv) ...
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... IP4059CX5/LF 4 100 k (10 k supply recommended) BUS 19.2 MHz 26 MHz 100 pF Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Comment - - Wafer-Level Chip-Scale Package (WLCSP); 1.34 mm 0.96 mm 0.41 mm; ESD IEC 61000-4-2 level contact air discharge ...
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... SHIELD RECEPTACLE 5 SHIELD 6 SHIELD SHIELD 8 IP4059CX5/LF D ESD C VBUS (1) Frequency is version dependent: ISP1505ABS: 19.2 MHz; ISP1505CBS: 26 MHz. Fig 26. Using the ISP1505 with a USB Host Controller; external 5 V source with built-in FAULT and external crystal V V CC(I/ bypass DATA1 1 C bypass C bypass DATA0 2 V ...
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V BUS USB MINI-B OR GND STANDARD-B 4 SHIELD RECEPTACLE SHIELD 6 IP4059CX5/LF SHIELD 7 B2 SHIELD 8 D ESD Fig 27. Using the ISP1505 with a Peripheral Controller; external 60 MHz ...
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... STANDARD-B 4 SHIELD RECEPTACLE SHIELD 6 IP4059CX5/LF SHIELD 7 B2 SHIELD 8 D ESD (1) Frequency is version dependent: ISP1505ABS: 19.2 MHz; ISP1505CBS: 26 MHz. Fig 28. Using the ISP1505 with a Peripheral Controller; external square wave input on pin XTAL1 V CC(I/O) C bypass V CC DATA1 1 C bypass C bypass DATA0 2 V CC(I/ RREF ...
Page 69
... 2.5 scale (1) ( 4.1 2.25 4.1 2.25 0.5 2.5 3.9 1.95 3.9 1.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver detail 0.5 2.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION SOT616 ISSUE DATE ...
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... Solder bath specifications, including temperature and impurities ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 01 — 19 October 2006 © NXP B.V. 2006. All rights reserved ...
Page 71
... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 30. Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Figure 30) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 ...
Page 72
... Magneto-Optical Non-Return-to-Zero Inverted On-The-Go Printed-Circuit Board Personal Digital Assistant [1] Physical Layer Packet Identifier Programmable Logic Device Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver peak temperature © NXP B.V. 2006. All rights reserved. time 001aac844 ...
Page 73
... USB Implementers Forum UTMI+ Low Pin Interface USB 2.0 Transceiver Macrocell Interface USB 2.0 Transceiver Macrocell Interface Plus Data sheet status Product data sheet Rev. 01 — 19 October 2006 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Change notice Supersedes - - © NXP B.V. 2006. All rights reserved. ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 19 October 2006 ISP1505A; ISP1505C © NXP B.V. 2006. All rights reserved ...
Page 75
... R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit allocation . . . . . . . . . . . . . . . . . . .49 Table 27. USB Interrupt Enable Rising Edge register ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description . . . . . . . . . . . . . . . . . . 50 Table 28. USB Interrupt Enable Falling Edge register (address R = 10h to 12h 10h 11h 12h) bit allocation ...
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... XTAL1 . . . . . .68 Fig 29. Package outline SOT616-1 (HVQFN24 .69 Fig 30. Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 01 — 19 October 2006 continued >> © NXP B.V. 2006. All rights reserved ...
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... ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.1 Synchronous mode 8.1.2 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 15 8.1.3 6-pin full-speed or low-speed serial mode . . . 16 8.1.4 3-pin full-speed or low-speed serial mode . . . 16 ISP1505A_ISP1505C_1 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 8.2 USB and OTG state transitions . . . . . . . . . . . 17 9 Protocol description . . . . . . . . . . . . . . . . . . . . 19 9.1 ULPI references . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 Power-On Reset (POR 9.3 Power-up, reset and bus idle sequence ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: ISP1505A_ISP1505C_1 All rights reserved. Date of release: 19 October 2006 ...