isp1302 NXP Semiconductors, isp1302 Datasheet - Page 33

• Manufacturer Part Number: isp1302
• Description: Isp1302 Universal Serial Bus On-the-go Transceiver With Carkit Support
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1302_1
Product data sheet
9.3.1 I
9.3.2 I
9.2 Interrupts
9.3 I
Table 45.
Any of the Interrupt Source register signals given in
when the signal becomes either LOW or HIGH. After an interrupt is generated, the SoC
should be able to read the status of each signal and the bit that indicates whether that
signal generated the interrupt. A bit in the Interrupt Latch register is set when any of the
following events occurs:
For detailed information, refer to The I
Table 46.
[1]
[2]
[3]
Table 47.
[1]
Bit
2
1
0
Bit
Symbol
Value
2
2
2
•
•
•
•
S
C-bus byte transfer format
C-bus device address
C-bus protocol
[1]
The corresponding bit in the Interrupt Enable High register is set, and the associated
signal changes from LOW to HIGH.
The corresponding bit in the Interrupt Enable Low register is set, and the associated
signal changes from HIGH to LOW.
The INT_N pin will be asserted if one or more bits in the Interrupt Latch register are
set. The INT_N pin will be de-asserted if all the bits in the Interrupt Latch register are
cleared by software.
S = Start.
A = Acknowledge.
P = Stop.
Determined by the status of the ADR/PSW pin on the rising edge of RESET_N. If ADR/PSW = HIGH,
bit A0 = 1; if ADR/PSW = LOW, bit A0 = 0. Bit A0 will be zero if there is no hardware reset pulse on the
RESET_N pin after power on.
Writing logic 1 to a set address sets the corresponding bit.
Symbol
DP_HI_IEH
SESS_VLD_IEH
VBUS_VLD_IEH
Byte 1
8 bits
Interrupt Enable High register (address S = 0Eh, C = 0Fh) bit description
I
I
2
2
C-bus byte transfer format
C-bus slave address bit allocation
A6
7
0
A
[2]
A5
Rev. 01 — 24 May 2007
6
1
Description
0 — Disable
1 — Enable
0 — Disable
1 — Enable
0 — Disable
1 — Enable
Byte 2
8 bits
A4
5
0
2
C-bus specification; ver. 2.1 .
A
[2]
A3
4
1
USB OTG transceiver with carkit support
Byte 3
8 bits
Table 38
A2
3
1
A
[2]
can generate an interrupt,
A1
2
0
..
..
© NXP B.V. 2007. All rights reserved.
ISP1302
A0
[1]
1
A
[2]
R/W
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X
0
P
[3]