mc33991dwr2 Freescale Semiconductor, Inc, mc33991dwr2 Datasheet - Page 12

• Manufacturer Part Number: mc33991dwr2
• Description: Gauge Driver Integrated Circuit
• Manufacturer: Freescale Semiconductor, Inc

synchronous, 16-bit serial synchronous interface data
transfer and four I/O lines associated with it: (SI, SO, SCLK,
and CS). The SI/SO pins of the 33991 follows a first in / first
CHIP SELECT (CS)
master device. When this pin is in a logic [0] state, the 33991
is capable of transferring information to, and receiving
information from, the master. The 33991latches data in from
the Input Shift registers to the addressed registers on the
rising edge of CS. The output driver on the SO pin is enabled
when CS is logic [0]. When CS is logic high, signals at the
SCLK and SI pins are ignored; the SO pin is tri-stated (high
impedance). CS will only be transitioned from a logic [1] state
to a logic [0] state when SCLK is a logic [0]. CS has an
internal pull-up (lup) connected to the pin as specified in the
Control I/O Table.
SERIAL CLOCK (SCLK)
33991device. The Serial Input (SI) pin accepts data into the
Input Shift register on the falling edge of the SCLK signal
while the Serial Output pin (SO) shifts data information out of
the SO Line Driver on the rising edge of the SCLK signal. It is
important the SCLK pin be in a logic [0] state whenever the
CS makes any transition. SCLK has an internal pull down
(Idwn), specified in the Control I/O Table. When CS is logic
behavior. To follow the explanations below, please refer to
the timing
12
Table 4. Data Transfer Timing
33991
33991 SPI INTERFACE AND PROTOCOL DESCRIPTION
INTRODUCTION
The SPI interface has a full duplex, three-wire
The Chip Select (CS) pin enables communication with the
SCLK clocks the Internal Shift registers of the
This section provides a description of the 33991 SPI
CS (1-to-0)
CS (0-to-1)
Pin
SO
SI
33991 SPI INTERFACE AND PROTOCOL DESCRIPTION
SO pin is enabled
33991 configuration and desired output states are transferred and executed according to the data in
the Shift registers.
Will change state on the rising edge of the SCLK pin signal.
Will accept data on the falling edge of the SCLK pin signal
DETAILED SIGNAL DESCRIPTIONS
FUNCTIONAL DESCRIPTION
INTRODUCTION
out (D15 / D0) protocol with both input and output words
transferring the most significant bit first. All inputs are
compatible with 5.0 V CMOS logic levels.
[1], signals at the SCLK and SI pins are ignored; SO is tri-
stated (high impedance). See the Data Transfer Timing
diagrams in Figures 2 and 3.
SERIAL INPUT (SI)
Serial Input (SI) information is read on the falling edge of
SCLK. A 16-bit stream of serial data is required on the SI pin,
beginning with the most significant bit (MSB). Messages not
multiples of 16 bits (e.g. daisy chained device messages) are
ignored. After transmitting a 16-bit word, the CS pin has to be
deasserted (logic [1]) before transmitting a new word. SI
information is ignored when CS is in a logic high state.
SERIAL OUTPUT (SO)
from the Shift register. The Status register bits will be the first
16-bits shifted out. Those bits are followed by the message
bits clocked in FIFO, when the device is in a daisy chain
connection, or being sent words of 16-bit multiples. Data is
shifted on the rising edge of the SCLK signal. The SO pin will
remain in a high impedance state until the CS pin is put into
a logic low state.
This pin is the input of the Serial Peripheral Interface (SPI).
The Serial Output (SO) data pin is a tri-stateable output
diagrams shown in Figures 4 and 5.
Description
Analog Integrated Circuit Device Data
Freescale Semiconductor