mc33991dwr2 Freescale Semiconductor, Inc, mc33991dwr2 Datasheet - Page 14

• Manufacturer Part Number: mc33991dwr2
• Description: Gauge Driver Integrated Circuit
• Manufacturer: Freescale Semiconductor, Inc

MODULE MEMORY MAP
by the three MSB of the 16-bit word received serially.
Functions to be controlled include:
• Individual gauge drive enabling
• Power-up/down
• Internal clock calibration
• Gauge pointer position and velocity
• Gauge pointer zeroing
• Individual gauge over temperature condition
• Battery out of range condition
• Internal clock status
• Confirmation of coil output changes should result in pointer
Table 2 provides the register available to control the above functions.
Table 5. Module Memory Map
REGISTER DESCRIPTIONS
Power, Enable, and Calibration Register (PECR)
disable the output drivers of the two gauge controllers.
illustrated in Figure 3. A write to the 33991 using this register
allows the master to independently enable or disable the
output drivers of the two gauge controllers as well as to
calibrate the internal clock, or send a null command for the
purpose of reading the status bits. This register is also used
to place the 33991 into a low current consumption mode.
• 0 = Disable
• 1 = Enable
14
33991
TIMING DESCRIPTIONS AND DIAGRAMS
COMMUNICATION MEMORY MAPS
Address [15:13]
Table 6. Power, Enable and Calibration Register (PECR)
Write
Various registers of the 33991 SPI module are addressed
Status reporting includes:
movement
This register allows the master to independently enable or
SI address 000 (Power, Enable, & Calibration Register is
These bits are write-only.
PE12—Null Command for Status Read
000
001
010
011
100
101
110
111
PE12
D12
Return to 0 Confirmation Register
Power, Enable, and Calibration
Maximum Velocity Register
Gauge 0 Position Register
Gauge 1 Position Register
D11
0
Return to 0 Register
Reserved for Test
Not Used
Register
Use
D10
0
D9
0
D8
0
POS0R
POS1R
RTZCR
Name
PECR
VELR
RTZR
Address: 000
D7
0
[1] to their assigned address bits, D0 and D1 respectively.
This feature could be useful to disable a driver if it is failing or
not being used. The device can be placed into a standby
current mode by writing a logic[0] to both D0 and D1. During
this state, most current consuming circuits are biased off.
When in the Standby mode, the internal clock will remain ON.
times defining the duration the motor will spend at each
microstep as it accelerates or decelerates to a commanded
position. The accuracy of the acceleration and velocity of the
motor is directly related to the accuracy of the internal clock.
Although the accuracy of the internal clock is temperature
independent, the non-calibrated tolerance is +70 to -35
percent. The 33991 was designed with a feature allowing
the internal clock to be software calibrated to a tighter
tolerance of ±10 percent, using the CS pin and a reference
time pulse provided by the micro controller.
[1] to D3. The calibration pulse must be 8 µs for an internal
clock speed of 1MHz, will be sent on the CS pin immediately
after the SPI word is sent. No other SPI lines will be toggled.
A clock calibration will be allowed only if the gauges are
disabled or the pointers are not moving, as indicated by
status bits ST4 and ST5.
pointer velocity and acceleration. Guaranteeing these
maximums requires the nominal internal clock frequency fall
below 1MHz. The frequency range of the calibrated clock will
always be below 1MHz if bit D4 is logic [0] when initiating a
calibration command, followed by an 8µs reference pulse.
The frequency will be centered at 1MHz if bit D4 is logic [1].
due to a lower motor gear reduction ratio. Writing a logic [1]
to bit D2 will slow the internal oscillator by one-third, leading
to a situation where it is possible to calibrate at maximum 667
kHz or centered at 667 kHz. In these cases, it may be
necessary to provide a longer calibration pulse of exactly 12
µs, without any indication of a calibration fault at status bit
ST7, as should be the case for 1 MHz if D2 is left logic [0].
D11: D0 will be ignored; this is referenced as the null
command and can be used to read device status without
affecting device operation.
valid PECR commands.
• 0 = Maximum f=1MHz (for 8us calibration pulse)
D6
0
Each of the gauge drivers can be enabled by writing a logic
The internal state machine utilizes a ROM table of step
Calibration of the internal clock is initiated by writing a logic
Some applications may require a guaranteed maximum
Some applications may require a slower calibrated clock
If bit D12 is logic [1] during a PECR command, the state of
PE11: PE5 These bits must be transmitted as logic [0] for
PE4—Clock Calibration Frequency Selector
D5
0
PE4
D4
Analog Integrated Circuit Device Data
PE3
D3
Freescale Semiconductor
PE2
D2
PE1
D1
PE0
D0