s1r72803f00a Epson Electronics America, Inc., s1r72803f00a Datasheet

no-image

s1r72803f00a

Manufacturer Part Number
s1r72803f00a
Description
Ieee1394 Link/ Transaction Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
s1r72803f00a2
Manufacturer:
EPSON
Quantity:
1 000
Part Number:
s1r72803f00a2
Manufacturer:
EPSON/爱普生
Quantity:
20 000
Part Number:
s1r72803f00a200
Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
DESCRIPTION
FEATURES
The S1R72803F00A is an IEEE Standard 1394-1995, P1394a Draft2.1 compliant LINK/Transaction Controller.
Since some of the transaction functions of this controller have become hardware, the later PageTable fetch and
data transmission can be executed automatically by setting the PageTable address and size in SBP-2.
In addition, thanks to a built-in MPU (SEIKO EPSON’s original 32-bit RISC processor S1C33) called a Flash
ROM which is necessary for the conversion system, the controller can provide peripheral devices with the
optimum 1394 interfaces by simply adding a Cable PHY Transceiver/Arbiter that complies with the standard.
LINK/Transaction Controller
• All interactive data transmissions in both asynchronous and isochronous transfer modes are supported.
• Stable interactive data transmissions of 100 Mbps, 200 Mbps and 400 Mbps of MaxPayload were made
• The hardware can detect IsocronousResourceManager automatically.
• Some of the transaction functions have become hardware to prevent the actual data transmission rate
• Communication with the upper layers has been simplified by separating the header and data partitions.
• The data partition has been subdivided into Stream and ORB partitions.
• A ring buffer is employed for the recipient header, recipient data (recipient Stream and recipient ORB
• The sizes of all partitions can be set freely.
• The busy state during data reception is controlled by the hardware automatically.
SBP-2 Support
By setting the PageTable address and size in SBP-2, the later Page Table fetch and data transmission can
be executed automatically.
PHY/LINK Interface
The P1394a is supported.
Transmission rate 100/200/400 Mbps are supported.
Isolation is supported (a bus holder is built in).
CPU
SEIKO EPSON’s original 32-bit Microsoft Controller Unit is built in.
Booting using both internal and external Flash ROMs is possible.
IDE Interface
PIO mode 0/1/2/3/4, Multiword DMA mode 0/1/2 and Ultra-DMA mode 0/1/2/3/4 are supported.
I/O baffer with 5V tolerance
Built-in SRAM
For the data packet : 8-Kbyte
For the MCU work : 8-Kbyte
Built-in Flash ROM
An 64-Kbyte Flash ROM is built-in.
3.3 V/ 5.0 V power supply
184-pin flat package (Pin pitch: 0.4 mm)
The package is not designed to be radiation-proof.
possible by the built-in SRAM.
from declining due to overhead (to secure the dedicated partition).
partitions) and sending data partitions.
IEEE1394 LINK/ Transaction Controller
S1R72803F00A
SBP-2 LINK Engine on chip
High-speed transfer(Ultra ATA66)
Built-in CPU and Flash
S1R72803F00A
PF1192-03
1

Related parts for s1r72803f00a

s1r72803f00a Summary of contents

Page 1

... IEEE1394 LINK/ Transaction Controller DESCRIPTION The S1R72803F00A is an IEEE Standard 1394-1995, P1394a Draft2.1 compliant LINK/Transaction Controller. Since some of the transaction functions of this controller have become hardware, the later PageTable fetch and data transmission can be executed automatically by setting the PageTable address and size in SBP-2. ...

Page 2

... S1R72803F00A BLOCK DIAGRAM XRESET U_AD<23:0> AD<23:00> U_DT<15:0> xCSREG<XCE4> xCSBUF<XCE7> DT<15:00> xCSFREG<XCE5> xCSFLS<XCE10> XCE10EX XCE9 XCE8 xINT(K65) XCE6 SLEEP(P33) XRD XWRL XWRH S1C33 Core BCLK XNMI X2SPDX ICEMD DSIO OSC3 OSC4 PLLC PLLS1 PLLS0 EA10MD2 EA10MD1 EA10MD0 2 U_AD<12:0> U_DT<7:0> xCSREG ...

Page 3

... Sequencer AyncTx FIFO IsoTx DMA for FIFO TRAN&SBP2 DMA for ATF/ TRAN&SBP2 ITF Control FIFO Register Register for for 1394 Tx/Rx TRAN&SBP2 Address Decoder/Data Syncronizer/Interrput Controller Internal Cpu Access I/F S1R72803F00A 1394 1394 PHY/LINK LINK&TRAN PHY/LINK control signal Core I/F Register for LINK&TRAN 3 ...

Page 4

... V 173 SS P10 174 DSIO 175 HV 176 DD XNMI 177 XRESET 178 ICEMD 179 INDEX V 180 SS HCLK 181 BCLK 182 N.C. 183 V 184 SS 4 EPSON S1R72803F00A TOP View N.C. 90 XHRST 89 HDD7 88 HDD8 87 HDD6 86 HDD9 85 HDD5 84 HDD10 HDD4 81 HDD11 80 HDD3 79 HDD12 ...

Page 5

... IDE address signal (MSB) IDE chip select signal IDE chip select signal IDE DASP signal IDE reset signal S1R72803F00A Remarks Try state output Drive capacity Schmidt input (bus holder) Try state output Drive capacity Schmidt input (bus holder) ...

Page 6

... S1R72803F00A Pin Name Pin No. I/O Reset SIC33 External Interface ( AD23 54 O AD22 53 O AD21 52 O AD20 51 O AD19 50 O AD18 49 O AD17 44 O AD16 43 O AD15 42 O AD14 41 O AD13 40 O AD12 39 O AD11 38 O AD10 36 O AD9 35 O AD8 34 O AD7 ...

Page 7

... Internal logic xInt monitor pin HIGH power supply (5V) 5,21,37,67,83,130,165,176 (8pins) LOW power supply (3.3V) 1,47,93,103,114,139 (6pins) GND 148,157,159,170,173,180,184 13,29,46,57,75,92,112,117,118,119,138(18pins) 2,45,48,91,94,137,140,172,183 (9pins) S1R72803F00A Remarks HIGH:Built-in flash boot mode LOW:External memory mode HIGH is fixed HIGH is fixed Built-in pull up resistors Remarks EXCLK_EN=Input when LOW PLL circuit can not be used Connect to GND N ...

Page 8

... S1R72803F00A DIMENSIONAL OUTLINE DRAWING Plastic QFP20-184 pin (S1R72803F00A) 139 184 NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products ...

Related keywords