S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet
S1K50000
Related parts for S1K50000
S1K50000 Summary of contents
Page 1
... MF1403-01 STANDARD CELL S1K50000 Series DESIGN GUIDE ...
Page 2
NOTICE No part of this material may be reproduced or duplicated in any from or by any means without the written permission of EPSON. EPSON reserves the right to make changes to this material without notice. EPSON does not assume ...
Page 3
New configuration of product number Starting April 1, 2001 the configuration of product number descriprions will be changed as listed below. To order from April 1, 2001 please use these product numbers. For further information, please contact Epson sales representative. ...
Page 4
... S1K50000 Series Table of Contents Chapter 1 Overview.................................................................................................. 1 1.1 Features........................................................................................................................ 1 1.2 Electrical Characteristics............................................................................................... 2 1.3 Outline of Standard-Cell Development Flow................................................................. 8 Chapter 2 Precautions on Circuit Design ............................................................ 10 2.1 Insertion of Input/Output Buffers ................................................................................. 10 2.2 Use of Differentiating Circuits Inhibited....................................................................... 10 2.3 Wired Logic Inhibited .................................................................................................. 10 2.4 Hazard Protection ....................................................................................................... 11 2.5 Fan-Out Limitations..................................................................................................... 11 2.6 Internal Bus Circuits.................................................................................................... 12 2.7 Bus Hold Circuits ........................................................................................................ 14 2.8 Precautions on Creating Circuit Diagrams (Logic Diagrams) ..................................... 15 2 ...
Page 5
... DD 9.3.4 HV -System Fail-Safe Cells .......................................................................................... 117 DD 9.4 Calculating the Delay Time in a Dual-Power-Supply System ...................................118 9.5 Notes on Calculating Power Consumption in a Dual-Power-Supply System............119 9.6 Estimating the Number of Power-Supply Pins in a Dual-Power-Supply System ......121 Appendix Release Note....................................................................................... 123 ii EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 6
... Chapter 1 Overview Seiko Epson’s S1K50000 series consists of high-function, high-integrated CMOS standard cells based on the 0.35-micron process. 1.1 Features • High degree of integration Maximum of 1,456,000 gates (2-input NAND gate equivalents) • Operating speed Internal gate: Input buffer: Output buffer: 2.12 ns (5.0 V typ.) using a level shifter, • ...
Page 7
... Rated Value *3 HV -0 -0 ± ± 50 OUT T -65 to 150 STG EPSON Unit °C Unit °C STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 8
... This applies to N-channel open-drain bidirectional buffers, as well as XIDC and XIDH input buffers. For Fail-Safe cells, a value acceptable. *2: This temperature range refers to the recommended ambient temperature in cases where [°C]. *3: This temperature range refers to the recommended ambient temperature in cases where Tj = -40 to 125 [°C]. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Symbol Min. ...
Page 9
... Lt — — — — — — — — — — — — — — fa EPSON STANDARD CELL S1K50000 SERIES Max. Unit 5.25 V 5.50 3. ° Max. Unit 3. ...
Page 10
... Low-Level Hold Current High-Level Reversing I Current Low-Level Reversing I Current Input-Pin Capacitance Output-Pin Capacitance Input/Output-Pin Capacitance *1: The values apply to cases where Ta = 0°C to 70°C. *2: Conforms to PCI standard Rev. 2.2 STANDARD CELL S1K50000 SERIES DESIGN GUIDE Table 1-5 Electrical Characteristics (HV DD Test Conditions I — — ...
Page 11
... STANDARD CELL S1K50000 SERIES DESIGN GUIDE Unit µA µA µ µA µA µA µ ...
Page 12
... Low-Level Reversing I Current Input-Pin Capacitance Output-Pin Capacitance Input/Output-Pin Capacitance *1: The quiescent current represents the typical value for each series 85°C. For details, see Tables 1-8 through 1-9. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Table 1-7 Electrical Characteristics ( Test Conditions I Static state DDS I — ...
Page 13
... Quiescent current between DDS temperature coefficient DDS DDS EPSON (Tj = 85°C) Unit Max. µA (Tj = 85°C) 2.0 V ± 0.2 V Unit Max. LI Max. DDS 31 to 230 µA and STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 14
... NG Overall evaluation OK ES (TS) approval notification ( ) Delivery- specification approval Those tasks enclosed are undertaken when requested by the customer. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Agent (interface) Development commencement Wiring diagram request Pin arrangement table • Timing waveform Simulation diagram file • Marking diagram ...
Page 15
... Because CMOS transistors are used, wired logic cannot be configured as in bipolar transistors. Therefore, the output pins of cells cannot be connected together, as shown in Figure 2-2. Output pins can only be connected together in a bus-circuit configuration. Figure 2-2 Example of Inhibited Wired Logic 10 EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 16
... Furthermore, for logic gates operating at high speed, such as high-speed clock lines (fmax = 40 MHz or more), make sure the output-pin capacitance of those gates is approximately half the fan-out limitation. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 2: Precautions on Circuit Design EPSON ...
Page 17
... Precautions on the use of bus circuits (1) Bus cells can only be used for bus circuits (for the S1K50000-series bus cells, see Table 2-1). (2) When using bus cells, add bus definition cells KBLT to the bus in the configuration of your circuit ...
Page 18
... The usable bus cells in the S1K50000 series are listed in Table 2-1. Cell Type Bus latches Bus driver Inverting bus driver Transparent latches with reset and 3-state output D-flip flops with rest and 3-state output 1-bit RAM Figure 2-3 Typical Configuration of a Bus Cell Circuit ...
Page 19
... Chapter 2: Precautions on Circuit Design 2.7 Bus Hold Circuits Available with the S1K50000 series are input/output buffers with a bus hold function to hold the input/output-pin data in order to prevent the output pins or bidirectional pins from entering a high-impedance state. However, because the retention capability of the bus hold circuit is repressed so as not to adversely affect normal bus operation, do not use the retained output as valid data ...
Page 20
... For diagram interfaces, circuit diagrams are normlly presented to Seiko Epson by the customer. In the creation of your circuit diagrams, note the following: • For the Seiko Epson format, use the logic symbols listed in “Standard Cell S1K50000-Series MSI Cell Library.” • Do not use the aslant wiring shown in the circuit diagram. ...
Page 21
... Note 3: The delay relative to the fan-out counts is only an approximate value for use as a guideline. [Restrictions and precautions] • Applicable series: S1L9000F, S1L30000, S1L35000, S1L50000, S1K50000 • The dedicated buffers can only be used for the purpose of Clock Tree Synthesis. • Clock Tree Synthesis can also be applied to data lines or other control signals. However, if the number of nets to which Clock Tree Synthesis is applied increases, a large skew or delay may result ...
Page 22
... Note 1: The target values are only approximate for use as guidelines in the application of synthesis, and it is not guaranteed that the values will be satisfied. Note 2: If you do not have definite target values, specify your desired values by entering a comment (e.g., “as small as possible”). STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 2: Precautions on Circuit Design Target Skew Value ...
Page 23
... Clock Tree Synthesis at Seiko Epson. Clock Root Figure 2-5 Customer’s Logic Circuit Clock Tree Synthesis Figure 2-6 Layout Diagram Derived by Applying Clock Tree Synthesis at Seiko Epson 18 KCRBF* Back annotation of delay EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 24
... ATPG tools helps to generate a test pattern that, for full-scan circuits, can attain a high fault detection rate of close to 100%, except for untestable nodes in which logical fault detection is impossible. Note that ATPG uses the full-scan method based on MUXSCAN-type flip- flops. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 2: Precautions on Circuit Design EPSON ...
Page 25
... A test pattern is generated in such a way that SA1 and SA0 are set for each node and that, when they are fixed to the observable logic level functional failure results. S-a-1 S-a-0/1 KOR2 Figure 2-7 Example of an Untestable Fault KDF KIN1 KDF XQ C EPSON STANDARD CELL S1K50000 SERIES S-a-0 KAD2 DESIGN GUIDE ...
Page 26
... TP generation registration ATPG rule check Pre-Simulation Auklet Post-ATPG check Fault-detection rate confirmation Post-simulation result confirmation Figure 2-8 ATPG Flow for Development by Auklet STANDARD CELL S1K50000 SERIES DESIGN GUIDE ATPG Tentative pin arrangement check sheet block diagram table Examination result Input pattern expected value ...
Page 27
... Sign-off EPSON Seiko Epson ATPG application notes Circuit ATPG rule check Circuit Pin layout Netlist data table ATPG ATPG rule check Scan insertion Fault-detection rate detection data P & & R Clock Tree Synthesis Post-Simulation STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 28
... However shared with bidirectional pins, make sure the pin is always in output state through the use of the ATPGEN pin, for example. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 2: Precautions on Circuit Design ...
Page 29
... Practical examples are shown below. If these measures are difficult to implement or there are any uncertainties about them, contact Seiko Epson. • Applicable series: S1L50000, S1L30000, S1L9000F, S1X50000, S1K50000 • Prepare one scan enable input pin (SCANEN dedicated input pin. ...
Page 30
... Make sure the bidirectional pins are set for input during scan shift mode unavoidable for the bidirectional pins to be assigned for scan data input or scan data output, fix the pins for input or output, respectively. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 2: Precautions on Circuit Design ...
Page 31
... For ATPG support, CTS (Clock Tree Synthesis) is essential during placement and routing. Therefore, please submit the necessary information for Clock Tree Synthesis specified on page 15, along with said information XBC1 A E SCANOUT XBC1 A E XBC1 EPSON STANDARD CELL S1K50000 SERIES D0 SCANIN D1 D2 DESIGN GUIDE ...
Page 32
... Note 1: If Yes, please correct your circuit, as the circuit cannot be scanned. Note 2: If No, please insert DFT, as the circuit cannot be scanned. In addition, if you would like to request DFT insertion by Seiko Epson because detailed circuit information is required in addition to this sheet, contact Seiko Epson. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 2: Precautions on Circuit Design EPSON ...
Page 33
... Pin name: ______________ Content of control, active level, etc. : _____________________________________________________ d. Pin name: ______________ Content of control, active level, etc. : _____________________________________________________ 28 rise • fall rise • fall rise • fall rise • fall rise • fall EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 34
... Note 3: If not inserted in the original circuit, please specify your desired contents. Note 4: Unless a specific request to the contrary is made, pins will be assigned by Seiko Epson. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 2: Precautions on Circuit Design : __________ : ____ % ...
Page 35
... INA[3:0]: A bus is used for an external pin name. INA[3]: A bus is used for an external pin name. Only alphanumeric characters, underscore '_', _[]_ (Verilog bus bracket), and _()_ (VHDL bus bracket) can be used. The string must always begin with a letter, however. EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 36
... STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 2: Precautions on Circuit Design ...
Page 37
... Before the Seiko Epson tools and utilities can be used, the VHDL format must be converted into Verilog format. For this reason, the Verilog reserved words specified in (12) also cannot be used in VHDL. 32 EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 38
... Usage Precautions 3.1 Types of Input/Output Buffers The S1K50000 series is available for many and varied types of cells, which can be chosen depending on the input interface level, the presence of Schmitt trigger inputs or pull-up/pull- down resistors, the output drive capability, and the noise protection measures used. In accordance with the descriptions below, choose the input/output buffers best suited for your circuit ...
Page 39
... Power Supply,” we will describe in detail the procedure for configuring the input and output buffers or bidirectional buffers with a single power supply. For details on the procedure for configuring the input and output buffers with dual power supplies, see Chapter 9, “Precautions on the Use of Dual Power Supplies.” 34 EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 40
... CMOS Schmitt CMOS Schmitt XIBHD Note: When value the pull-up/pull-down resistance values correspond to 1:120 k , 2:240 k respectively. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 3: Types of Input/Output Buffers and Usage Precautions Table 3-1-1 Input Buffers Function With or without pull-up/pull-down resistors ...
Page 41
... Chapter 3: Types of Input/Output Buffers and Usage Precautions 3.2.1.2 Output-Buffer Configuration with a Single Power Supply Tables 3-2-1 and 3-2-2 list the S1K50000-series output buffers. A Output signal TA Used for testing TS XOB1T (a) Normal output buffer Figure 3-1 Example of an Output-Buffer Symbol 36 Output signal Enable Output Used for the output-buffer test ...
Page 42
... *** In addition to the output buffers specified in Table 3-2-1, a configuration without test pins may be considered. If such a configuration is desired, contact Seiko Epson or its distributor. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 3: Types of Input/Output Buffers and Usage Precautions Table 3-2-1 Output Buffers -0.1 mA ...
Page 43
... V) EPSON ( Cell Name*** OH XOBST XOBMT XOB1T XOB2T XOB3T XOB1CT XOB2CT XOB3AT XOB3BT XTBST XTBMT XTB1T XTB2T XTB3T XTB1CT XTB2CT XTB3AT XTB3BT XTBMHT XTB1HT XTB2HT XTB3HT XTB1CHT XTB2CHT XTB3AHT XTB3BHT STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 44
... Bidirectional-Buffer Configuration with a Single Power Supply Tables 3-3-1 and 3-3-2 list the S1K50000-series bidirectional buffers. Output signal Used for testing Figure 3-2 Example of a Bidirectional-Buffer Symbol STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 3: Types of Input/Output Buffers and Usage Precautions Input signal A Enable E TA ...
Page 45
... XBC1CHT XBC2CHT -12 mA XBC3AHT -12 mA XBC3BHT XBHMHT XBH1HT XBH2HT -12 mA XBH3HT XBH1CHT XBH2CHT -12 mA XBH3AHT -12 mA XBH3BHT STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 46
... In addition to the bidirectional buffers specified in Table 3-3-2, a configuration with pull-up/pull-down resistors or without test pins may be considered. If such a configuration is desired, contact Seiko Epson or its distributor. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 3: Types of Input/Output Buffers and Usage Precautions Table 3-3-2 Bidirectional Buffers Function = 2 ...
Page 47
... Chapter 3: Types of Input/Output Buffers and Usage Precautions 3.2.2 Fail-Safe Cells (1) Outline Seiko Epson’s S1K50000 series of Fail-Safe cells allows signals operating at levels higher than the power-supply voltage in a single-power-supply design to be interfaced without the installation of a dedicated interfacing power supply. Therefore not necessary for customers to install the operating power supply or an interfacing power supply in the LSI conventionally required ...
Page 48
... Fail-Safe cell cannot have its output pulled high through the addition of a pull-up resistor external to the standard cell. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 3: Types of Input/Output Buffers and Usage Precautions side eliminated. This input buffer ...
Page 49
... Seiko Epson or its distributor. 44 Table 3-4-2 Fail-Safe Output Buffers N-channel open-drain XOD1T 6 mA XOD2T 12 mA XOD3T 2 mA XOD1CT 6 mA XOD2CT 3.3 V) EPSON (V DD Cell Name Tri-state XTBF1 XTBF2 — XTBF1C XTBF2C — XTBF3A STANDARD CELL S1K50000 SERIES DESIGN GUIDE = 3.3 V) ...
Page 50
... If such a test-pinless configuration is desired, contact Seiko Epson or its distributor. Used for testing Figure 3-3 Example of an N-channel Open-Drain Bidirectional-Buffer Symbol STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 3: Types of Input/Output Buffers and Usage Precautions Function Input signal ...
Page 51
... BB1CP1 BB1CP2 BB2CD1 BB2CD2 BB2CP1 BB2CP2 BB3AD1 BB3AD2 BB3AP1 BB3AP2 BG1D1 BG1D2 — — BG2D1 BG2D2 — — BG1CD1 BG1CD2 — — BG2CD1 BG2CD2 — — BG3AD1 BG3AD2 BG3AP1 BG3AP2 5 V 5-V output 3.3-V output 3.3-V output 5-V input STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 52
... XLIN and XLOUT Oscillator cell XLIN PAD Internal to the IC Rf X’tal Cg For continuous oscillation Figure 3-5 Method for Configuration of an Oscillator Circuit STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 3: Types of Input/Output Buffers and Usage Precautions XLOT XLIN PAD ...
Page 53
... Because the oscillator cell is connected to the LV system power supply, use the input and output cells labeled “XLLIN” and “XLLOT,” with the letter “L” prefixed to XLIN and XLOT. 48 and either side of those input/output pins. SS EPSON - DD STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 54
... Gated I/O Cells 3.4.1 Outline of Gated I/O Cells Seiko Epson’s S1K50000 series of Gated I/O cells make it possible to provide input to pins in the floating or Hi-Z state without the use of pull-up or pull-down circuits, an operation that was conventionally impossible. They also make it possible to cut off the high-voltage-side (HV power supply in a multi-power-supply design. Two types are available: one in which the power ...
Page 55
... Pull- 100 100 k XBA1D2T XBA1P1T XBA1P2T XBA2D2T XBA2P1T XBA2P2T XBA3D2T XBA3P1T XBA3P2T XBA1D2 XBA1P1 XBA1P2 XBA2D2 XBA2P1 XBA2P2 XBA3D2 XBA3P1 XBA3P2 XBA1CD2 XBA1CP1 XBA1CP2 XBA2CD2 XBA2CP1 XBA2CP2 XBA3AD2 XBA3AP1 XBA3AP2 XBA3BD2 XBA3BP1 XBA3BP2 STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 56
... Drain Test Latch Level Type Function Function Available N/A CMOS Normal N/A N/A *1: The indicated resistance values apply to cases where V STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 3: Types of Input/Output Buffers and Usage Precautions Table 3-5-4 Gated Bidirectional Cells Output Without a Speed Current Resistor (mA ...
Page 57
... Type 5.0 V Only Pull-down Pull- 120 120 k XHBA4D1T XHBA4D2T XHBA4P1T XHBA4P2T XHBA4AD1T XHBA4AD2T XHBA4AP1T XHBA4AP2T XHBA4BD1T XHBA4BD2T XHBA4BP1T XHBA4BP2T XHBA4D1 XHBA4D2 XHBA4P1 XHBA4P2 XHBA4AD1 XHBA4AD2 XHBA4AP1 XHBA4AP2 XHBA4BD1 XHBA4BD2 XHBA4BP1 XHBA4BP2 STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 58
... Input Drain Test Level Type Function Available CMOS Normal N/A *1: The indicated resistance values apply to cases where HV STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 3: Types of Input/Output Buffers and Usage Precautions Table 3-5-7 Gated Bidirectional Cells Output Output Without a Latch Speed Current Resistor Function ...
Page 59
... KAO24A User Logic KAO24A KAO24A KAO24A TEST1 MS KAD3 TM0 TD TM1 TE TM2 TS TST TAC ILG OLG KTCIR EPSON BIDIR3 TE TS XHBA1T BIDIR2 TE TS XHBT1T A BIDIR1 E XBB1 A BIDIR0 E XBB1 A OUT1 TA TS XHOB1T A OUT0 TA TS XHOB1T STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 60
... LSI’s internal signals to be monitored. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 4: Circuit Design Taking Testability into Account ...
Page 61
... Chapter 4: Circuit Design Taking Testability into Account 4.3 Circuit Configuration to Facilitate DC and AC Tests 4.3.1 Configuration of a Test Circuit The S1K50000 series requires a test-circuit configuration allowing DC and AC tests to be conducted efficiently. If such a test circuit is not configured in your circuit design, contact Seiko Epson or its distributor for confi ...
Page 62
... Create a test-mode control circuit (KTCIR), and include it in the circuit design. g. Make sure the input buffer (XITST1) for the test-mode switch pin has its output pins X and LG connected to the TST and ILG pins of the KTCIR. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 4: Circuit Design Taking Testability into Account : 1 pc ...
Page 63
... INP1 INP2 • Input-characteristic (V TSTEN Measured pin *1 Unmeasured pin *1: Apply to all input and bidirectional pins, except for TESTEN High /V ) measurement mode High . . . Low . . . High/low input . . . Low /V ) measurement mode High . . . High/low input . . . High EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 64
... In such a case, make sure the input level of the test pin (e.g., TSTEN) is low (= 0). d. When the input level of the test pin (e.g., TSTEN) is high (= 1), all of the pull-up/pull- down resistors are disabled (inactive). STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 4: Circuit Design Taking Testability into Account ...
Page 65
... TM0 TD TM1 TM2 TS TST TAC ILG OLG I_2 Figure 4-1 Example of a Test Circuit EPSON A OUT1 TA TS XOB1T OUT2 TE TS XTB1T A E BID1 XBC1T A OUT3 TA TS XOB1T A OUT4 TA TS XOB1T TAC OLG STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 66
... EOF Note: A period (.) denotes Figure 4-2 Example of a Test Pattern Created for a Test Option STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 4: Circuit Design Taking Testability into Account (High) (Input low) ; Pull-up/down off ; AC path output (high), other outputs (low) ...
Page 67
... Existing test patterns at Seiko Epson are used. Please note, however, that the test patterns for the functional cells (i.e., the existing test patterns) cannot be disclosed to customers install a test circuit EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 68
... Particularly when using two or more of the same functional cell, assign the functional-cell names a sequential number in the drawing, clearly indicating for which functional cell the test pin is used. (4) Clearly indicate the method for switching to test mode. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 4: Circuit Design Taking Testability into Account EPSON ...
Page 69
... For ASICs, the package’s thermal resistance and the power consumption vary with each circuit and application. Therefore, strictly speaking, specification examination based difficult result, delay libraries are available with Seiko Epson’s S1K50000 series to help you verify the circuit design at its early stage with respect to the approximate guidelines given below [° ...
Page 70
... Note 1: The delay in a predriver with a level shifter cannot be obtained simply by multiplying the Typ. value by a dispersion coefficient of delay, as described above. Precalculated Min. and Max. values are listed along with the Typ. values in the “Standard Cell S1K50000-Series MSI Cell Library.” See Section 9.4, “Calculating the Delay Time in a Dual-Power-Supply System,” in this manual. ...
Page 71
... EPSON STANDARD CELL S1K50000 SERIES Usage Use this to multiply the Typ. values of T and 5.0 V. Use this to multiply the Typ. values of T and 3.3 V. Use this to multiply the Typ. ...
Page 72
... KNA2 KNO2 The fan-in values for KIN2, KNA2, and KNO2 are given in Table 5-2. Their sum is the value of Load A. Load A (N1) = (Fa n KIN2 Fan - KNA2) STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 5: Propagation Delay Time and Timing Design 2.0 KIN 1 ...
Page 73
... The assumed wiring capacitance of each master is listed in the “Standard Cell S1K50000-Series MSI Cell Library.” 5.5 Calculating the Propagation Delay Time The following shows an example of the calculation of the propagation delay time using the circuit shown in Figure 5-2 (operating at 3 ...
Page 74
... (4) Path STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 5: Propagation Delay Time and Timing Design Output Pin Fan-out From X 8 (KIN1 (Load A + Load 15.0 (4+2) = 131 (ps ...
Page 75
... C L For details on the nonloaded and loaded delay coefficients of output cells, see the “Standard Cell S1K50000-Series MSI Cell Library.” 5.7 Flip-Flop Setup and Hold Times The signal timing applied by flip-flops and an MSI sequential circuit consisting of flip-flops play an important role in the proper operation of the configured circuit with the intended logic. The fl ...
Page 76
... RESET DATA SETUP RELEASE ( (SETUP Figure 5-4 Timing Waveform Diagram 1 (explanation diagram for (1) through (5)) STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 5: Propagation Delay Time and Timing Design Figure 5-3 KDFSR HOLD ...
Page 77
... Figure 5-5 Timing Waveform Diagram 2 (explanation diagram for (6) through (7)) The flip-flop setup/hold times of the S1K50000 series are listed in cell libraries in the form shown in Table 5-4 below. During actual use, please see the timing characteristics of each individual cell. Table 5-4 Timing Characteristics of KDFSR (Reference) ...
Page 78
... This is known as the “skew.” This skew may make it impossible for the setup or hold time to be met. Take this skew into consideration in the design of a circuit, to ensure a sufficient timing allowance. The intra-chip skews in the S1K50000 series are listed in Table 5-5 below. Cell Internal cell ...
Page 79
... It also allows a delay to be inserted, as with NRZ. Test rate waveform Output waveform Strobe Figure 6-1 Limitations on Timing Settings 74 Input delay Pulse width Waveform EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 80
... N), and no other combinations for the same pin in one test pattern. For bidirectional pins waveform can only be entered in cases in which the output state is nonexistent. These pins are handled in the same way as for input pins. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 6: Creating Test Patterns ...
Page 81
... To this end, all of the conditions specified below must be met. In addition, events in which the quiescent current can be measured must be set at two or more locations DDS EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 82
... V these states for the measured pin, this test cannot be performed. The input-current test is further classified into the following categories: STANDARD CELL S1K50000 SERIES DESIGN GUIDE (high) voltage to the measured pin while it is held low, the DD voltage to the pin ...
Page 83
... ,” and is guaranteed by the maximum current value. For this test to ,” and is guaranteed by the maximum current value. For this test voltage is applied to it, respectively. Therefore, the test pattern EPSON DD STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 84
... For an intermittently oscillating circuit, therefore, observe the following not use an RZ waveform for the input signal not change the clock signal by changing the state of the enable signal. STANDARD CELL S1K50000 SERIES DESIGN GUIDE X G ...
Page 85
... Do not specify a path that passes through any other bidirectional cell between the measured path’s input buffer and the output buffer. (4) If there are two or more working voltage ranges, make sure the measured voltages in the AC test are both within one of such voltage ranges. 80 EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 86
... In such a case, if the letter “Z” is detected in bidirectional pins with pull-up/down resistors, customers will also be requested to correct the test pattern for the reasons described above. The same applies to bidirectional pins with open-drain output. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 6: Creating Test Patterns ...
Page 87
... Input/Output Mode Simulation Input Mode Input Mode Input Mode EPSON Simulation Result (Output Pattern) “X” “?” “1” “1” “0” “0” STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 88
... Total i o int To calculate the power consumption in a dual-power-supply system, see Chapter 9, “Precautions on the Use of Dual Power Supplies.” STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 7: Estimating Power Consumption , is expressed by the equation Total P : power consumption in the input buffer power consumption in the output buffer ...
Page 89
... Table 7-1 Input Cell Kpi in the S1K50000 Series (2) Power consumption of output buffers (P The power consumption of output buffers differs between DC loads (resistive loads, such as when the counterpart to be connected TTL device) and AC loads (capacitive loads, such as when the counterpart to be connected CMOS device). ...
Page 90
... DC DCH i=1 Thus, the power consumption (Po) of the output buffer i i=1 STANDARD CELL S1K50000 SERIES DESIGN GUIDE | ( ( ( Figure 7-1 Typical Duty Cycle ) / DCL Duty ...
Page 91
... Cell), although the propagation delay time increases slightly. When using low-power cells, halve the S1K50000-series K in the calculation of the power consumption. The low-power cells are flip-flop cells with names suffixed by “X0,” and cells with names suffi ...
Page 92
... CFLGA239 62.2 CFLGA152 63.3 CFLGA104 64.3 STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 7: Estimating Power Consumption ) (°C) Cu-L/F 2 m/sec 3 m/sec PKG PIN j-a j QFP5 QFP5 100 – – QFP5 128 – – QFP8 ...
Page 93
... For more information, contact Seiko Epson or its distributor. 8.2 Simultaneously Operating Buffers and Added Power Supply The S1K50000-series cells have a large output drive capability mA result, the output buffers generate a large amount of noise during operation, and an extremely large amount during simultaneous operation. ...
Page 94
... PCI Table 8-2 Number Number of buffers Output drive operating capability ( simultaneously 4 mA STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 8: Pin Arrangement and Simultaneous Operation Power Supplies Added for Simultaneous Operation of Output Buffers Number of power supplies to add ...
Page 95
... Number of power supplies to add EPSON ( 100 pF C 200 2 100 pF C 200 STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 96
... When it is decided which package to use, determine the pin arrangement on the package. For the power-supply pins and the number of usable input/output pins on each package of the S1K50000 series, refer to the designated “Pin Arrangement Table.” When the pin arrangement is decided, send a “Pin Arrangement Table” to Seiko Epson after specifying the pin arrangement on the designated sheets. At Seiko Epson, placement & ...
Page 97
... Because this noise is generated primarily by the equivalent inductance L2, the greater the rapidity of the power-supply current, the larger the amount of noise generated stipulate the rated amount of current that is allowed to fl EPSON power- SS STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 98
... The most efficient means of reducing overshoot and undershoot is the use of output cells with a small drive capability. As the load capacitance increases, overshoot and undershoot tend to decrease. Therefore, caution is required, particularly when output cells with a large drive capability are used. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 8: Pin Arrangement and Simultaneous Operation V ...
Page 99
... High speed input Figure 8-3 Example of the Placement of Critical Signal Pins – Output pins pins Bid High speed output Through input Through output EPSON , not place output pins DD SS STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 100
... Choose pull-up/pull-down resistors with resistance values as small as possible. Figure 8-5 Example of the Placement of Pull-Up/Pull-Down Pins – 1 PULL DOWN Figure 8-6 Example of the Placement of Pull-Up/Pull-Down Pins – 2 STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 8: Pin Arrangement and Simultaneous Operation V SS ...
Page 101
... When using large-current drivers, place power-supply pins near their pins to secure the power supply needed for such drivers (Figure 8-9). 96 Simultaneously changing output pins A OUT1 TA TS XOB3T DL1 A OUT2 TA TS XOB3T = 12 mA, 24 mA, PCI), observe the OL EPSON STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 102
... The TAB suspended pins are the package pins that are connected directly to the LSI substrate. These pins are at the V external sources. Normally, leave these pins open when they are mounted on the board. These pins are indicated by “##” in the pin arrangement table. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 8: Pin Arrangement and Simultaneous Operation V ...
Page 103
... Bidirectional pins and other output pins are placed on the lower side. 98 Input pins Bid pins Output pins EPSON V SS SOUT 0 SOUT 1 SOUT SOUT 3 SOUT SOUT 5 SOUT SOUT 7 SOUT 8 SOUT STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 104
... MOSC HOUT OUT01 V All Edges STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 8: Pin Arrangement and Simultaneous Operation Explanation of Pin Detailed Explanation of the Position of Each Pin Name Input pins with pull ups Located where the impact of noise is the least. Input pins for the clock Located near the center of the package, and near power supply pins ...
Page 105
... Chapter 9: Precautions on the Use of Dual Power Supplies Chapter 9 Precautions on the Use of Dual Power Supplies The S1K50000 series supports a dual-power-supply system (5.0 V and 3 3.3 V and 2.0 V), allowing input/output buffers to be individually interfaced with a signal of 5 2.0 V. The internal cell area operates with a single power supply of 3 2.0 V. ...
Page 106
... S1K50000-series usage example with two power supplies Figure 9-1 S1K50000-Series Usage Example with Two Power Supplies 9.3 Dual-Power-Supply-Type Input/Output Buffers When operating with a dual-power-supply system, use dedicated dual-power-supply input/ output buffers. Be aware that single-power-supply input/output buffers cannot be used in a dual-power-supply system. Therefore, single-power-supply input/output buffers cannot be used in combination with dedicated dual-power-supply input/output buffers ...
Page 107
... Buffer Buffer Pull-up resistor (120 k , 240 k ) Buffer Pull-down resistor (120 k , 240 k ) Buffer Buffer Pull-up resistor (120 k , 240 k ) Buffer Pull-down resistor (120 k , 240 k ) EPSON . -system input buffers are DD ( Without Without Without ( Without Without STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 108
... LV -System Output Buffers DD The available types of S1K50000-series LV and 9-2-2. Function Normal output Output for PCI Normal output for high speed Normal output for low noise 3-state output 3-state output for PCI 3-state output for high speed 3-state output for low noise 3-state output for (Bus hold circuit) ...
Page 109
... XLOB3AT XLOB3BT XLTBST XLTBMT XLTB1T XLTB2T XLTB3T XLTB3AT XLTB3BT XLTBMHT XLTB1HT XLTB2HT XLTB3HT XLTB3AHT XLTB3BHT STANDARD CELL S1K50000 SERIES DESIGN GUIDE = 2.0 V) ...
Page 110
... LV -System Bidirectional Buffers DD The available types of S1K50000-series LV 9-3-1 and 9-3-2. Table 9-3-1 LV Input Level Bi-directional output LVTTL Bi-directional output for high speed Bi-directional output for low noise PCI Bi-directional output for PCI Bi-directional for low noise output LVTTL Schmitt Bi-directional output for high speed ...
Page 111
... XLBH3BT 0 -0.3 mA XLBCMHT 0 -0.6 mA XLBC1HT XLBC2HT XLBC3HT XLBC3AHT XLBC3BHT 0 -0.3 mA XLBHMHT 0 -0.6 mA XLBH1HT XLBH2HT XLBH3HT XLBH3AHT XLBH3BHT STANDARD CELL S1K50000 SERIES DESIGN GUIDE = 2.0 V) ...
Page 112
... 3 addition to those listed in Table 9-4-2, cells without test pins are available. If the use of such cells is desired, contact Seiko Epson or its distributor. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 9: Precautions on the Use of Dual Power Supplies Table 9-4-1 Fail-Safe Input Buffers Pull-down ...
Page 113
... XLBDH2T 12 mA XLBDH3T 2 mA XLBDH1CT 6 mA XLBDH2CT ( Pull-down Pull- 100 100 k XLBB1D1 XLBB1D2 XLBB1P1 XLBB1P2 XLBB2D1 XLBB2D2 XLBB2P1 XLBB2P2 XLBG1D1 XLBG1D2 — — XLBG2D1 XLBG2D2 — — — — — — = 3.3 V) STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 114
... Note: When value the pull-up/pull-down resistance values correspond to 1: 2:120 k respectively. *1 signifies the cell dedicated to HV STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 9: Precautions on the Use of Dual Power Supplies -system input circuit, and the next stage is configured with an ...
Page 115
... Pull-down resistor ( 120 k ) Table 9-6-2 Input-Level Shifters Fuction With or without pull-up/down resistor Buffer Buffer Pull-down resistor (100 k , 200 k ) Buffer Buffer Pull-down resistor (100 k , 200 k ) EPSON ( Without Without Without ( Without Without ( Without Without STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 116
... HV -System Output Buffers DD The available types of S1K50000-series HV through 9-8-2. Function Normal output Output for PCI Normal output for high speed Normal output for low noise 3-state output Output for PCI 3-state output for high speed 3-state output for low noise 3-state output (Bus hold circuit) ...
Page 117
... XHOB2T XHOB3T PCI-3V XHOBPBT XHOB3AT XHOB3BT XHTBST XHTBMT XHTB1T XHTB2T XHTB3T PCI-3V XHTBPBT XHTB3AT XHTB3BT XHTBMHT XHTB1HT XHTB2HT XHTB3HT XHTB3AHT XHTB3BHT STANDARD CELL S1K50000 SERIES DESIGN GUIDE = 3.3 V) ...
Page 118
... For N-channel open-drain output buffers, in addition to those listed in Table 9-8-2, use of a configuration without test pins may be considered. If the use of such a configuration is desired, contact Seiko Epson or its distributor. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 9: Precautions on the Use of Dual Power Supplies -System N-Channel Open-Drain Output Buffers ...
Page 119
... Chapter 9: Precautions on the Use of Dual Power Supplies 9.3.3.3 HV -System Bidirectional Buffers DD The available types of S1K50000-series HV 9-9-1 through 9-10-2. Table 9-9-1 HV Input Level Bi-directional output TTL Bi-directional output for high speed Bi-directional output for low noise Bi-directional output CMOS Bi-directional output for high speed Bi-directional output for low noise ...
Page 120
... For bidirectional buffers, in addition to those listed in Table 9-9-1, use of bidirectional buffers configured with pull-up/pull-down resistors or without test pins may be considered. If the use of a configuration without test pins is desired, contact Seiko Epson or its distributor. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 9: Precautions on the Use of Dual Power Supplies ...
Page 121
... XHBCMHT XHBC1HT XHBC2HT -12 mA XHBC3HT -12 mA XHBC3AHT -12 mA XHBC3BHT XHBHMHT XHBH1HT XHBH2HT -12 mA XHBH3HT -12 mA XHBH3AHT -12 mA XHBH3BHT STANDARD CELL S1K50000 SERIES DESIGN GUIDE = 3.3 V) ...
Page 122
... For N-channel open-drain bidirectional buffers, in addition to those listed in Table 9-10-2, use of bidirectional buffers configured without test pins may be considered. If the use of a configuration without test pins is desired, contact Seiko Epson or its distributor. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 9: Precautions on the Use of Dual Power Supplies ...
Page 123
... Because a highly accurate delay-time calculation environment is provided, please note that the delay calculations are not in agreement with those performed using the values listed in the “Standard Cell S1K50000-Series MSI Cell Library.” When calculating the delay time in input and output buffers, use the T K (Typ ...
Page 124
... V) in order to calculate the power consumption in each system. The Kp the respective power-supply voltages are listed in Table 9-11 below STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 9: Precautions on the Use of Dual Power Supplies DD ) and Pi (LV DD system is represented ...
Page 125
... For the K pint ( ( EPSON )) DD ), and that of the Duty Duty H} OH value for the values to use, see Table pint , is obtained from the following Total ) + P DD int STANDARD CELL S1K50000 SERIES DESIGN GUIDE system in pint ...
Page 126
... DD For the number of power-supply pins to add, see Tables 8-1-1 through 8-2-2 for the 3.3-V or 2.0-V system, and Tables 9-12 and 9-13 for the 5.0-V system. STANDARD CELL S1K50000 SERIES DESIGN GUIDE Chapter 9: Precautions on the Use of Dual Power Supplies and LV ...
Page 127
... EPSON ( 100 pF CL 200 ( 100 pF CL 200 STANDARD CELL S1K50000 SERIES DESIGN GUIDE ...
Page 128
... A * SYSTEM CLOCK STROBE POINT RATE (ns) • DELAY (ns) A • B • C • • • STANDARD CELL S1K50000 SERIES DESIGN GUIDE WAVEFORM A.P RATE A.P = ACTIVE POINT (SYSTEM CLOCK) COMMENT Duty EPSON Appendix: Release Note TYPE NRZ NRZ NRZ NRZ NRZ STROBE A.P 123 ...
Page 129
... International Sales Operations AMERICA EPSON ELECTRONICS AMERICA, INC. - HEADQUARTERS - 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 - SALES OFFICES - West 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 Fax: +1-310-955-5400 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. ...
Page 130
In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings. ...
Page 131
... S1K50000 Series DESIGN GUIDE This manual was made with recycle papaer, and printed using soy-based inks. ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue May, 2001 Printed in Japan C A ...