S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 20

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

2.8 Precautions on Creating Circuit Diagrams (Logic Diagrams)
2.9 Clock Tree Synthesis
STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
For diagram interfaces, circuit diagrams are normlly presented to Seiko Epson by the
customer. In the creation of your circuit diagrams, note the following:
• For the Seiko Epson format, use the logic symbols listed in “Standard Cell S1K50000-Series
• Do not use the aslant wiring shown in the circuit diagram.
• To write input/output and bidirectional pin names, use 2 to 32 alphanumeric characters
(1) Outline
(2) Method of practice
MSI Cell Library.”
beginning with an English letter.
Clock Tree Synthesis is a service that automatically inserts a tree of a set of buffers with
optimized clock line skew and delay. In some cases, clock trees are inserted by the
customers themselves for the purpose of clock line fan-out adjustment or the like.
However, because in such a case trees are automatically placed and routed by P&R tools,
the clock line may, in effect, have an increased clock skew. In addition, wiring delay may
eventually be increased to a greater extent than predicted, as placement & routing and cell
delays are often imbalanced. Clock Tree Synthesis solves all of these problems efficiently.
Before a clock tree can be automatically inserted, the clock line must have a dedicated
buffer inserted by the customer for the following three purposes:
Choose the dedicated buffer for Clock Tree Synthesis from the table of dedicated buffers
provided later. When inserting the selected dedicated buffer, handle it the same way as
with ordinary cells by referring to the “image diagram,” in consideration of the “restrictions
and precautions.” In addition, for logic-synthesis-based design, because the dedicated
buffer cannot be automatically inserted, write the procedure using description language
directly. At that time, execute the command specified below to ensure that another buffer
will not be synthesized on the clock line in which the dedicated buffer has been inserted:
• Determination of the location at which to apply Clock Tree Synthesis
• Performance of a preliminary routing-level simulation (pre-simulation) through
• Back annotation of the delay in the inserted clock tree to allow the performance of
set_dont_touch_net net_name
estimation of the delay in the inserted clock tree
precise post-simulation
EPSON
Chapter 2: Precautions on Circuit Design
15