s1r72902 Epson Electronics America, Inc., s1r72902 Datasheet

s1r72902

Manufacturer Part Number

s1r72902

Description

Ieee1394 Av/c-compliant Integrated One-chip Controller

Manufacturer

Epson Electronics America, Inc.

Datasheet

1.S1R72902.pdf (4 pages)

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The S1R72902F00A is a digital AV system controller that contains an IEEE1394 interface and a stream interface

conforming to the IEEE 1394-1995 and 1394a-2000 standards.

This single-chip IC integrates a 2-port cable PHY, a LINK/Transaction controller ideal for IEC61883 Isochronous

packets, Seiko Epson’s original 32-bit RISC processor, and a Flash memory for storing firmware.

For IEC61883 Isochronous packet transfer, this IC can add and remove CIP and source packet headers

automatically. The stream interface can connect to separate 8-bit DMA interfaces for inputs and outputs.

Part of transactions is hardware-implemented. Setting PageTable addresses and sizes in the SBP-2 protocol

automates subsequent PageTable fetch and data transfer.

The S1R72902F00A provides an optimal IEEE1394 interface to AV appliances from computer peripherals to

digital home electronics.

Rev.1.0

IEEE1394 AV/C-Compliant Integrated One-Chip Controller

DESCRIPTION

FEATURES

Cable PHY Transceiver/Arbitor

Link/Transaction Controller

IEC61883-compliant Isochronous packet transfer

SBP-2 Support

Stream interface (supporting IDE interfaces)

C33 RISC CPU

Contains a two-port small-amplitude differential transceiver that excels in precision and speed.

The on-chip 400MHz PLL enables transmission and reception at S400, S200 and S100 speeds and

50MHz SCLK output.

The Cable Power Status function detects a cable power drop.

Supports bi-directional data transfer in both Asynchronous and Isochronous modes.

The built-in SRAM implements stable bi-directional data transfer at a MaxPayload of up to

100/200/400Mbps.

Simplifies communications with upper layers by separating header and data areas.

The packet buffer area is divided into header, stream, and ORB areas.

Each of the receive header area, receive data areas (receive stream and receive ORB areas), and

transmit data area (transmit stream area) has a ring buffer. These areas can be configured to any size.

Busy conditions during reception are automatically controlled by the hardware.

The receive header area is divided into Isochronous and Asynchronous areas.

Asynchronous command packet transfer during Isochronous packet transmission.

In Asynchronous data reception, the command packets and data packets can be identified according to

the transaction label, and stored separately in the receive Stream area and the receive ORB area.

Automatically transmits up to eight packets with CIP and source packet headers.

Automatically separates the received Isochronous packets into headers (Isochronous packet header,

CIP header, and source packet header) and AV data, and stores them separately in the receive header

and receive stream areas.

Receives the packets in a specific format by identifying the FMT code in the CIP header.

Once PageTable addresses and sizes in the SBP-2 protocol are set, subsequent PageTable fetch and

data transfer are done automatically.

The stream interface can connect to separate 8-bit DMA interfaces for inputs and outputs, but they

cannot be used simultaneously for bi-directional data transfer.

Capable of outputting Sync (synchronous byte signals) for IEC61883-compliant Isochronous packets.

The IDE interface can be switched to the stream interface supporting PIO 0-4, Multi-ward DMA 0-2, and

Ultra DMA 0-4 modes.

A 5V tolerant cell is used to operate the IC as a 3.3V single power supply.

Equipped with Seiko Epson’s original RISC CPU, this IC does not require an extra CPU.

SEIKO EPSON CORPORATION

S1R72902

This enables

PF1318-02

Related parts for s1r72902

s1r72902 Summary of contents

Page 1

... IEEE1394 AV/C-Compliant Integrated One-Chip Controller DESCRIPTION The S1R72902F00A is a digital AV system controller that contains an IEEE1394 interface and a stream interface conforming to the IEEE 1394-1995 and 1394a-2000 standards. This single-chip IC integrates a 2-port cable PHY, a LINK/Transaction controller ideal for IEC61883 Isochronous packets, Seiko Epson’s original 32-bit RISC processor, and a Flash memory for storing firmware. ...

Page 2

... S1R72902 External CPU interface This IC has 18 address lines, 16 data lines, a read strobe, and a write H/L strobe for an external C33 RISC CPU. Flash ROM This IC contains a 64kbyte Flash ROM. There’s no need for additional Flash ROMs. ICD33 Interface This IC reserves six pins as an interface with ICD33 that facilitates the development of firmware for the internal CPU ...

Page 3

... EPSON S1R72902 θ Dimension in inches* Nom. Max. (0.945) (0.948) (0.945) (0.948) (0.066) (0.004) (0.055) (0.059) (0.020) (0.008) (0.011) (0.005) (0.006) (10°) (0.020) (0.027) (0.039) (0 ...

Page 4

... S1R72902 NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products ...

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