lan9117 Standard Microsystems Corp., lan9117 Datasheet - Page 121

• Manufacturer Part Number: lan9117
• Description: Lan9117 High-performance Single-chip 10/100 Non-pci Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9117
6.2
SYMBOL
t
t
cycle
t
t
t
t
t
csdv
t
t
asu
don
doff
doh
csh
nCS, nRD
csl
ah
A[7:1]
Data Bus
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
Note: The “Data Bus” width is 16 bits
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycles.
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Figure 6.1 LAN9117 PIO Read Cycle Timing
Table 6.3 PIO Read Timing
DATASHEET
121
MIN
45
32
13
0
0
0
0
TYP
Revision 1.5 (07-11-08)
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns