lan9117 Standard Microsystems Corp., lan9117 Datasheet - Page 31

• Manufacturer Part Number: lan9117
• Description: Lan9117 High-performance Single-chip 10/100 Non-pci Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9117
3.6
3.6.1
3.6.2
3.7
MODE OF OPERATION
Mode 0
Mode 1
(WORD_SWAP—Word Swap Control
(WORD_SWAP—Word Swap Control
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
It should be noted that Magic Packet detection can be performed when LAN9117 is in the D0 or D1
power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the
D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when
the device enters the D1 state.
Bus Writes
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit write). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next write is performed to the other word. If a write to the
same word is performed, the LAN9117 disregards the transfer.
Bus Reads
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit read). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next read is performed from the other word. If a read to the
same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The
LAN9117 will reset its read counters and restart a new cycle on the next read.
The SMSC LAN9117 supports “Big-Endian” or “Little-Endian” processors with 16-bit bus interfaces. To
support big-endian processors, the hardware designer must explicitly invert the layout of the byte
lanes. The
Mapping".
Additionally, please refer to
additional information on status indication on Endian modes.
Host Bus Operations
Big and Little Endian Support
A1 = 0
A1 = 1
WORD_SWAP—Word Swap Control
D[15:8]
Byte 3
Byte 1
DATA PINS
Table 3.7 Byte Lane Mapping
Section 5.3.17, "WORD_SWAP—Word Swap Control," on page 90
equal to FFFFFFFFh)
not equal to FFFFFFFFh)
DATASHEET
Byte 2
Byte 0
D[7:0]
31
must be set correctly following
Note:
This mode can be used by 32-bit
processors operating with an external 16-
bit bus.
DESCRIPTION
Table 3.7, "Byte Lane
Revision 1.5 (07-11-08)
for