lan9117 Standard Microsystems Corp., lan9117 Datasheet - Page 41

• Manufacturer Part Number: lan9117
• Description: Lan9117 High-performance Single-chip 10/100 Non-pci Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9117
3.10.2.3
3.10.3
3.10.3.1
Denotes a level-triggered "sticky" status bit
PME_TYPE
PME_POL
PME_IND
PME_EN
phy_int
WUEN
WUFR
MPEN
MPR
Power Managment Event Indicators
Figure 3.11
pme_interrupt signals. The pme_interrupt signal is used to set the PME_INT status bit in the INT_STS
register, which, if enabled, will generate a host interrupt upon detection of a power management event.
The PME_INT status bit in INT_STS will remain set until the internal pme_interrupt signal is cleared
by clearing the WUPS bits, or by clearing the corresponding WOL_EN or ED_EN bit. After clearing the
internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a ‘1’ to this bit in the
INT_STS register. It should be noted that the LAN9117 can generate a host interrupt regardless of the
state of the PME_EN bit, or the external PME signal.
The external PME signal can be setup for pulsed, or static operation. When the PME_IND bit in the
PMT_CTRL register is set to a ‘1’, the external PME signal will be driven active for 50ms upon
detection of a wake-up event. When the PME_IND bit is cleared, the PME signal will be driven
continously upon detection of a wake-up event. The PME signal is deactivated by clearing the WUPS
bits, or by clearing the corresponding WOL_EN or ED_EN bit. The PME signal can also be deactivated
by clearing the PME_EN bit.
Internal PHY Power-Down Modes
There are 2 power-down modes for the internal Phy:
General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the internal PHY, except the
management interface, is powered-down and stays in that condition as long as Phy register bit 0.11 is
HIGH. When bit 0.11 is cleared, the PHY powers up and is automatically reset. Please refer to
5.5.1, "Basic Control Register," on page 109
is a simplified block diagram of the logic that controls the external PME, and internal
Figure 3.11 PME and PME_INT Signal Generation
WOL_EN
ED_EN
WUPS
WUPS
DATASHEET
50ms
41
PME_INT_EN
for additional information on this register.
PME_INT
Other System
Interrupts
LOGIC
IRQ_EN
PME
Revision 1.5 (07-11-08)
Section
IRQ