peb20590 Infineon Technologies Corporation, peb20590 Datasheet

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Edition 2001-03-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms ...

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PEB 20590, PEB 20591 PRELIMINARY Revision History: 2001-03-01 Previous Version: 01.00 Page Subjects (major changes since last revision) Page 15 Pull-ups for the signals TMS, TDI, TRST Page 34 ID-Code for TAP controller Page 29 Maximum wander tolerance Page 35 ...

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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 5.6 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures Figure 1 Top-Level Block Diagram of the VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure ...

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List of Tables Table 1 VIP Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Preface This document provides reference information on VIP Organization of this Document This Data Sheet is divided into 9 chapters organized as follows: • Chapter 1, Introduction Gives a general description of the VIP, lists the key features, ...

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PRELIMINARY Your Comments We welcome your comments on this document. We are continuously trying to improve our documentation. Please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (VIP), device ...

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PRELIMINARY 1 Introduction This chapter gives a general overview of the VIP including a top-level block diagram and the logic symbol diagram, it lists the key features, and presents some typical applications. 1.1 Overview VIP (Versatile ISDN Port ...

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PRELIMINARY The VIP is available in two different versions, which differ in the possible interface combinations: Table 1 VIP Product Family Device Available Interfaces VIP PEB 20590 Four channels are programmable to either S the other four channels ...

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PRELIMINARY Versatile ISDN Port VIP, VIP-8 Version 2.1 1.2 VIP Key Features VIP is a universal ISDN transceiver IC for different interface modes (S • Eight 2B+D line interfaces with full duplex transceivers – S/T interfaces at ...

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PRELIMINARY 1.3 Logic Symbol Diagrams 24 S/T and U PN Line Interface 6 Dedicated Pins Figure 2 Logic Symbol PEB 20590 ( Pins used) 32 S/T and U PN Line Interface 6 Dedicated Pins Figure 3 Logic Symbol ...

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PRELIMINARY 1.4 Typical Applications Typical VIP applications are PBX line cards (U The following figures illustrate sample configurations in which the VIP shows its flexibility. • S S/T ...

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PRELIMINARY • Central Office Figure 6 DELIC-PB and VIP Card for 8/16 S/T Interfaces Data Sheet VIP-8 PEB 20591 (optional) DELIC-PB PEB 20571 VIP-8 PEB 20591 IOM-2000 Memory ...

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PRELIMINARY 2 Pin Description The VIP is available in an 80-pin Plastic Metric Quad Flat Package (P-MQFP-80-1). This chapter presents a simple layout of the 80-pin MQFP package with pin and signal callouts and a table of signal definitions. 2.1 ...

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PRELIMINARY (top view) 60 SR5b/LI5b 61 SR5a/LI5a V DDA V 64 SSA SX5b SX5a V DDA V 68 SSA SX6a SX6b V SSA V 72 DDA SR6a/LI6a SR6b/LI6b SR7b/LI7b SR7a/LI7a 76 V DDA V SSA SX7b SX7a ...

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PRELIMINARY 2.2 Pin Descriptions Table 2 PEB 20590: U Pin Symbol In (I) No. Out(O) 25 SR1a/LI1a I / I/O 26 SR1b/LI1b 39 SR3a/LI3a 40 SR3b/LI3b 62 SR5a/LI5a 61 SR5b/LI5b 76 SR7a/LI7a 75 SR7b/LI7b 12 LI0a I/O 13 LI0b 28 ...

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PRELIMINARY Table 3 PEB 20591: U Pin Symbol In (I) No. Out(O) 12 SR0a/LI0a I / I/O 13 SR0b/LI0b 25 SR1a/LI1a 26 SR1b/LI1b 27 SR2a/LI2a 28 SR2b/LI2b 39 SR3a/LI3a 40 SR3b/LI3b 48 SR4a/LI4a 47 SR4b/LI4b 62 SR5a/LI5a 61 SR5b/LI5b 73 ...

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PRELIMINARY Table 4 IOM-2000 Interface Pin Symbol In (I) No. Out (O) 18 FSC I 19 DCL_2000 CMD I 3 STAT O 4 REFCLK O Data Sheet During Function Reset I IOM-2000 ...

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PRELIMINARY Table 5 Clock Signals and Dedicated Pins Pin Symbol In (I) No. Out (O) 42 CLK15 CLK15 INCLK I 33 VIP_ADD0 I 34 VIP_ADD1 16 IDDQ I 41 POWDN I 5 DIR O 60 SCANEN ...

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PRELIMINARY Table 6 Power Supply and Reset Pin Symbol In (I) No. Out (O) 11, 24 DDA 29, 38, 49, 63, 67 DDD 45, 53 10, 23 SSA 30, 37, ...

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PRELIMINARY 3 Interface Description The VIP provides four types of external interfaces: U interfaces, an IOM-2000 interface and a JTAG boundary scan test interface. These interfaces are described in the following sections: 3.1 Overview of Interfaces The VIP provides the ...

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PRELIMINARY • The time between the end of reception of a frame from the TE and the beginning of transmission of the next frame by the LT must be greater than the minimum guard time. The guard time in TE ...

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PRELIMINARY Control and Maintenance Bits Bit Description LF Framing Bit Always logical ‘1’. M M-Bit Final bit of the frame. Four successive M-bits compose a superframe. Three signals are carried in this superframe: CV Code Violation Bit First bit of ...

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PRELIMINARY • Figure 10 AMI Coding on the U Scrambling / Descrambling B-channel data on the U PN subscriber terminal gets enough pulses for a reliable clock extraction (flat continuous power density spectrum), and to avoid periodical patterns on the ...

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PRELIMINARY 3.2.2 U Transceiver PN The receiver input stages consist of an amplifier/equalizer, followed by a peak detector adaptively controlling the thresholds of the comparators and a digital oversampling unit. LIa LIb Figure 11 Transceiver Functional Blocks Amplitude Figure 12 ...

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PRELIMINARY To enable the filter of equalizer inside the VIP, set bit TICCMR:FIL to ’1’ (please refer to VIP channel config description in DELIC-LC/-PB SW User’s Manual). The adaptive amplifier control of the equalizer should be set to automatic. Set ...

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PRELIMINARY . Figure 13 Receive Signal Oversampling on U 3.3 S/T Line Interface The functionality is compatible with that of QUAT-S (PEB 2084). External protection circuitry is reduced, and 1:1 transformers are required. Data Sheet Interface Description Interface PN 22 ...

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PRELIMINARY 3.3.1 Frame Structure The S/T interface uses two pairs of copper wires (dedicated to transmit and receive) for 2B+D data transfer. It builds a direct link between the VIP and connected subscriber terminals or the Central Office. It supports ...

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PRELIMINARY Bit Description A Activation Bit A = (0b) → INFO 2 transmitted A = (1b) → INFO 4 transmitted S S-Channel Data Bit S1 and S2 channel data M Multiframing Bit M = (1b) → Start of new multi-frame ...

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PRELIMINARY 3.3.2 S/T Transceiver Receiver Characteristics The receiver input stages consist of a differential amplifier, followed by a peak detector and a set of comparators. Additional noise immunity is achieved by digital oversampling after the comparators, meaning that the sampling ...

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PRELIMINARY 3.3.3.1 LT-S Mode In the LT-S mode, the DELIC is the clock master to all terminals connected to the VIP. In receive direction, two cases are distinguished, depending on the bus configuration: • Point-to-point or extended passive bus • ...

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PRELIMINARY 3.3.3.2 LT-T Mode • Programmed by DELIC IOM-2000 Command bits: MOSEL (1:0) = ’00’, MODE(2:0) = ’001’ • In LT-T applications, the VIP/DELIC system operates as slave to the central office clock. • The 192-kHz receive bit timing is ...

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PRELIMINARY Jitter Requirements In LT-T mode, ITU-T I.430 specifies a maximum jitter in transmit direction of – resulting in 730 ns peak-to-peak. This specification will be met by the VIP provided that the master ...

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PRELIMINARY 3.3.5 Receive Signal Oversampling The receive signal is oversampled within the receive clock period, and a majority logic is used to reduce the bit error rate in severe conditions. • As illustrated in Figure 19, each received bit is ...

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PRELIMINARY 3.4 IOM-2000 Interface Overview The IOM-2000 interface connects up to three VIPs to DELIC. DELIC as the communication controller performs parts of the layer-1 protocol, which enables flexible and efficient operation of the VIP. Note: For detailed description of ...

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PRELIMINARY 3.4.1 IOM-2000 Frame Structure 3.4.1.1 Data Interface On the ISDN line side of the VIP, data is ternary coded. Since the VIP contains logic to detect the level of the signal, only the data value is transferred via IOM-2000 ...

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PRELIMINARY FSC DCL F-bit ...

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PRELIMINARY FSC DCL F-bit ...

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PRELIMINARY 3.5 JTAG Boundary Scan Test Interface The VIP provides IEEE 1149.1-compatible boundary scan support to allow cost-effective board testing. It consists of: • Complete boundary scan test • Test access port (TAP) controller • Five dedicated pins: TCK, TMS, ...

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PRELIMINARY INTEST . INTEST supports internal chip testing. When the TAP controller is in the state “update DR”, all inputs are updated internally with the falling edge of TCK. When it has entered state “capture DR” the levels of all ...

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PRELIMINARY 4 Operational Description After some general remarks on the operation of the DELIC & VIP chipset, the reset and the initialization procedure are described. The operation of analog test loops as well as the monitoring of illegal code violations ...

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PRELIMINARY 4.4 Analog Test Loops Different analog test loops may be switched in the VIP near to the S interfaces. No external U PN • Transparent analog loop, data forward path enabled • Non-transparent analog loop, data forward ...

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PRELIMINARY 5 Electrical Characteristics This chapter contains the DC and AC specifications (as far as available) and timing diagrams. 5.1 Absolute Maximum Ratings Parameter Storage temperature IC supply voltage DC input voltage (except I/Os) DC output voltage (including I/Os); output ...

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PRELIMINARY 5.3 DC Characteristics V = 3.3 V ± 0. 70° Table 11 DC Characteristics Parameter Symbol All digital pins except LIna,b; SXna,b; SRna,b; CLK15-I,-O L-input voltage V IL H-input voltage V IH ...

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PRELIMINARY Table 11 DC Characteristics (cont’d) Parameter Symbol I Transmitter output X current Transmitter output Z X impedance 1) Nominal value determined by fuses 2) Absolute current limit resulting from the S interface specification CLK15-I H-input voltage V IH L-input ...

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PRELIMINARY 5.4 Capacitances ° 3.3 V ± 0. Table 12 I/O Capacitances (except line interfaces and clocks) Parameter Pin capacitance 5.5 Recommended 15.36-MHz Crystal Parameters The user has two options to ...

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PRELIMINARY 5.6 AC Characteristics 70° 3.3 V ± 0. Note: Timing measurements are made at 2.0 V for a logical 1’ and at 0.8 V for a logical ’0’. Figure 24 ...

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PRELIMINARY 5.9 IOM-2000 Interface • ...

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PRELIMINARY Table 14 IOM-2000 Interface Timing Parameter Symbol FSC setup time before DCL_2000 rising edge FSC hold time after DCL_2000 falling edge DX setup time before DCL_2000 falling edge DX hold time after DCL_2000 falling edge 5.10 JTAG Boundary Scan ...

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PRELIMINARY Table 15 JTAG Boundary Scan Timing Values Parameter Test clock period Test clock period low Test clock period high TMS setup time to TCK TMS hold time from TCK TDI setup time to TCK TDI hold time from TCK ...

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PRELIMINARY 6 Application Hints This chapter provides some additional information on how to use the VIP. The first section describes some external circuitry: Recommended line transformers, resistors and capacitors. Different wiring configurations in user premises are depicted for the LT- ...

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PRELIMINARY 6.1.2 U Interface External Circuitry PN A transformer, external resistors and two capacitors (100 nF and 0.33 µF) are connected externally to the line interface pins LIna,b. Voltage overload protection is achieved by adding clamping diodes (see VIP U ...

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PRELIMINARY Transmitter. Dedicated external resistors (10 … 12.5 Ω) are required for the transmitter in order to • Adjust the output voltage to the pulse mask (nominal 750 mV according to ITU-T I.430), • Meet the output impedance of a ...

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PRELIMINARY 6.2 Wiring Configurations in LT-S Mode • < 1000 m SCOUT-S TR TE1 < 100-200 < 10m SCOUT-S ... TE1 500 m < 25- < 10m SCOUT-S ... TE1 TE8 Figure 32 Wiring ...

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PRELIMINARY 6.3 Loop Modes The following figure shows the different loops that can be closed in the VIP. Loops are programmed by the DELIC using the command bits LOOP, EXLP and TX_EN. • VIP External Circuitry Analog Line TX Driver ...

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Package Outlines • P-MQFP-80-1 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet Package Outlines Dimensions ...

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PRELIMINARY 8 Glossary • AMI Alternate Mark Inversion ANSI American National Standardization Institute CMOS Complementary Metal Oxide Semiconductor CO Central Office DC Direct Current DECT Digital European Cordless Telecommunication DELIC DSP Embedded Line and Port Interface Controller (PEB 20570, PEB ...

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PRELIMINARY 9 Index A AC characteristics 42 Analog test loops 37 Application hints 46 Applications 7 B Block diagram 4 C Capacitances 41 Clock synchronization 25 Crystal parameters characteristics 39 E Extended passive bus 26 External circuitry ...

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PRELIMINARY S/T transceiver 25 Receive clock recovery Receiver characteristics S/T transformer 46 S/T transmitter performance Short passive bus 26 System integration 7 T TAP controller coding line interface 16 PN Control and maintenance bits ...

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