peb20550 Infineon Technologies Corporation, peb20550 Datasheet - Page 224

• Manufacturer Part Number: peb20550
• Description: Extended Pcm Interface Controller
• Manufacturer: Infineon Technologies Corporation

The following register bits are used in conjunction with the PCM input comparison
function:
PCM Mode Register
PMOD:
AIC1 … 0:
Interrupt Status Register
ISTA:
The ISTA register should be read after an interrupt in order to determine the interrupt
source. In connection with the PCM comparison function one maskable (MASK) interrupt
bit is provided by the EPIC:
PIM:
Semiconductor Group
bit 7
bit 7
PMD1
TIN
Alternative Input Comparison 1 and 0.
AIC0 set to logical 1 enables the comparison function between RxD0
and RxD1.
AIC1 set to logical 1 enables the comparison function between RxD2
and RxD3.
AIC1, AIC0 set to logical 0 disables the respective comparison
function.
In PCM mode 2, AIC0 must be set to logical 0.
PCM Input Mismatch; this bit is set to logical 1 immediately after the
comparison logic has detected a mismatch between a pair of PCM
input lines. The exact reason for the interrupt can be determined by
reading the PICM register. Reading ISTA clears the PIM bit. A new
PIM interrupt can only be generated after the PICM register has been
read.
PMD0
SFI
MFFI
PCR
MAC
PSM
224
read/write reset value:
read
AIS1
PFI
reset value:
AIS0
PIM
Application Hints
AIC1
SIN
00
00
PEB 2055
H
H
PEF 2055
bit 0
bit 0
AIC0
SOV