adm1075-2aruz-rl7 Analog Devices, Inc., adm1075-2aruz-rl7 Datasheet
adm1075-2aruz-rl7
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adm1075-2aruz-rl7 Summary of contents
Page 1
... PMBUS 12-BIT ADC FET POWER FOLDBACK CONTROL FAULT TIMER GATE CONTROL CURRENT LIMIT VEE_G SS VEE Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ADM1075 LATCH GPO1/ALERT1/CONV DC-TO-DC GPO2/ALERT2 CONVERTER C SDAO LOAD SDAI SCL ADR ADC_AUX PWRGD DRAIN PLIM ...
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... Power Monitor Commands ...................................................... 32 Warning Limit Setup Commands ............................................ 33 PMBus Direct Format Conversion .......................................... 34 Voltage and Current Conversion Using LSB values .............. 35 ADM1075 Alert Pin Behavior ...................................................... 36 Faults and Warnings .................................................................. 36 Generating an Alert ................................................................... 36 Handling/Clearing an Alert ...................................................... 36 SMBus Alert Response Address ............................................... 37 ...
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... Initial Version Read EIN_EXT Register ............................................................49 Read VAUX Register...................................................................50 VAUX OV Warn Limit Register................................................50 VAUX UV Warn Limit Register................................................50 VAUX Status Register .................................................................50 Outline Dimensions........................................................................51 Ordering Guide ...........................................................................51 Rev Page ADM1075 ...
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... V rail to save shunt power dissipation (see the Powering the ADM1075 section for more details). A full-scale current limit can be selected by choosing the appropriate model. The maximum current limit is set by the combination of the sense resistor, R voltage on the ISET pin, using external resistors ...
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... V GATE V ≥ GATE 0 V ≤ VIN ≤ GATE V ≤ for ADM1075-1, per individual pin; SENSE V ≤ 130 mV for ADM1075-2, per individual pin SENSE − I ΔSENSEx SENSE+ SENSE− 0 ≤ I ≤ 100 μ μF VCAP ...
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... Constant Power Active Circuit Breaker Offset, V CBOS Severe Overcurrent Voltage Threshold, V SENSEOC Response Time Glitch Filter Duration Total Response Time ADM1075-2 ONLY (GAIN = 25) Hot Swap Sense Voltage Hot Swap Sense Voltage Current Limit, V SENSECL Constant Power Active Circuit Breaker Offset, V CBOS ...
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... ISET SS SENSE = 0V SS reaches this level enabled, ramping; SENSE ADM1075-1 only (gain = 50) SS reaches this level enabled, ramping; SENSE ADM1075-2 only (gain = 25 0.5 V TIMER ≤ TIMER = 0.5 V TIMER = 0.5 V TIMER > 1.65 V ISET ≤ PLIM = 1 ÷ ...
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... Leakage Current PWRGD PIN Output Low Voltage, V OL_PWRGD VIN That Guarantees Valid Output Leakage Current CURRENT AND VOLTAGE MONITORING Current Sense Absolute Error (ADM1075-1) Current Sense Absolute Error (ADM1075-2) ADC_V/ADC_AUX Absolute Accuracy ADC Conversion Time Power Multiplication Time Min Typ Max Unit ...
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... No connect state; maximum leakage current allowed Connect to VCAP VCAP; must not exceed the maximum ADR allowable current draw from VCAP mA, SDAO only OL Device is not powered ±10% Unit Test Conditions/Comments kHz μs μs μs μ μs μ 3 SU;STO S P ADM1075 ...
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... ADM1075 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN Pin to VEE UVL Pin to VEE UVH Pin to VEE OV Pin to VEE ADC_V Pin to VEE ADC_AUX Pin to VEE SS Pin to VEE TIMER Pin to VEE VCAP Pin to VEE ISET Pin to VEE SPLYGD Pin to VEE LATCH Pin to VEE RESTART Pin to VEE ...
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... GPO2/ALERT2 12 17 ADR GPO1/ALERT1/CONV 13 16 SHDN 14 15 RESTART Figure 3. Pin Configuration PWRGD of the MOSFET. This is used for DS , sets an initial timing cycle delay and a fault delay. The GATE pin TIMER Rev Page voltage of the FET. As the PLIM voltage changes, the DS ADM1075 ...
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... ADM1075 Pin No. Mnemonic Description 16 General-Purpose Digital Output (GPO1). GPO1/ ALERT1 /CONV Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or warning conditions have been detected. Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC sampling cycle begins ...
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... TEMPERATURE (°C) Figure 8. V Low vs. Temperature (I GATE GATE 14 12 0µA 10 5µ –40 – TEMPERATURE (°C) Figure 9. V High vs. Temperature GATE ADM1075 85 100 115 85 100 115 = 100 μA) 100 120 ...
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... ADM1075 –50 –35 –20 – TEMPERATURE (°C) Figure 10. I Pull-Down vs. Temperature GATE (V) GATE Figure 11. I Pull-Down vs. V GATE 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 – ...
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... TEMPERATURE (°C) Figure 20. PLIM Current Clamp vs. Temperature 3.0 2.5 2.0 1.5 1.0 0.5 0 –50 –35 –20 – TEMPERATURE (°C) Figure 21. VCAP vs. Temperature (I = 100 μA) VCAP ADM1075 85 100 115 85 100 115 85 100 115 ...
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... ADM1075 UVH 1000 UVL 800 600 400 200 0 –50 –35 –20 – TEMPERATURE (°C) Figure 22. UVx Threshold vs. Temperature 1000 800 600 400 200 0 –50 –35 –20 – TEMPERATURE (°C) Figure 23. OV Threshold vs. Temperature 100 SENSE– 0 SENSE+ – ...
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... ADM1075-1 ISET = 1.65V ISET = 1.25V ISET = 1.0V ISET = 0.75V ISET = 0.25V ISET = 0.125V 100 115 ADM1075 100 115 Rev Page ADM1075-2 +85°C 45 ADM1075-2 +25°C ADM1075-2 –40°C 40 ADM1075-1 +85°C ADM1075-1 +25°C 35 ADM1075-1 –40° 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 V ...
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... Figure 34. Severe OC Threshold vs. Temperature, ADM1075-1, ISET = 1.65 V 100 225% 90 200 150% 60 125 –50 –35 –20 – TEMPERATURE (°C) Figure 35. Severe OC Threshold vs. Temperature, ADM1075-2, ISET = 1. 225 150% 30 125% 20 ISET UNDEFINED IN GREY AREA 10 0 0.25 0.45 0.65 0.85 1.05 ISET (V) Figure 36. Severe OC Threshold vs. ISET 100 ...
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... Data Sheet 00 DECODE 01 DECODE 3.0 2.5 2.0 1.5 1.0 0.5 0 –25 –20 –15 –10 –5 I (µA) ADR Figure 40. V vs. I ADR ADR 10 DECODE 11 DECODE 0 5 Rev Page ADM1075 ...
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... SHUNT IN _ MAX SHUNT _ MIN MAX SHUNT _ MIN MAX R SHUNT voltage is supplied by the GS –48V RTN R SHUNT C LOAD VIN 1µF GATE VEE ADM1075 SENSE+ SENSE– VEE Figure 41. Powering the ADM1075 Data Sheet I MAX Q1 R SENSE ...
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... The value of the averaging resistors is chosen to be much greater than the trace resistance between the sense resistor terminals and the inputs to the ADM1075. This greatly reduces the effects of differences in the trace resistances. C LOAD ...
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... ISET pin, the resistor ISET = (V × 50) for ADM1075-1 or ISET SENSE = (V × 25) for ADM1075-2 ISET SENSE is the sense voltage limit. The VCAP rail can also SENSE ADM1075 for the ADM1075-2. When ) reaches the circuit breaker voltage − SENSECL CBOS × ...
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... FET is allowed to spend based on matching this time TIMER is connected to the backplane supply, the internal IN ADM1075 must be charged up. A very short time ADM1075 then goes through an initial ADM1075 1µs 10µs 100µs 1ms 10ms DC 1000 GATE I IN ...
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... TIMERH TIMER = ( V − × μA) OFF TIMERH TIMERL TIMER features a very fast detection circuit that quickly monitors the supply voltage for undervoltage + × TOP BOTTOM OV RISING THRESHOLD R BOTTOM ≈ − × μA ) FALLING RISING TOP Data Sheet ADM1075 ...
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... The input threshold This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details. Rev Page ADM1075 Hot Swap Fault Retry section for ...
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... An averaging function is provided for voltage and current that allows a number of samples to be averaged by the ADM1075. This function reduces the need for postprocessing of sampled data by the host processor. The number of samples that can be ...
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... Some extra care is required if using the the ADuM3200. If the power at the secondary side is enabled by the ADM1075, the iso Power solution may not work. Because iso Power is unpowered in this case, the in an undefined state. If the SHDN input comes from the ...
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... If the PEC byte sent during a write transaction is incorrect, it ignores the command (does not execute it) and sets a status flag. Within a group command, the host can choose to send or not send a PEC byte as part of the message to the ADM1075. Rev Page Data Sheet ADM1075 ...
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... Data Sheet SMBus MESSAGE FORMATS Figure 54 to Figure 62 show all the SMBus protocols supported by the ADM1075, along with the PEC variant. In these figures, unshaded cells indicate that the bus host is actively driving the bus; shaded cells indicate that the ADM1075 Figure 54 to Figure 62 use the following abbreviations: ...
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... Using a group command possible, for example, to turn multiple PMBus devices on or off at the same time. In the case of the ADM1075 also possible to issue a power monitor command that initiates a conversion, causing multiple devices to sample together at the same time. This is analogous ...
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... DEVICE_CONFIG Command The DEVICE_CONFIG command is used to configure certain settings within the ADM1075, for example, to modify the duration of the severe overcurrent glitch filter and to set the trip threshold. This command is also used to configure the polarity of the second IOUT current warnings. ...
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... They can also be used to set a GPO mode on the pin, so that it is under software control. If this mode is set, the SMBAlert masking bits are ignored. On the ADM1075, one of the inputs can also be configured as a hardware-based convert control signal. If this mode is set, the GPO and SMBAlert masking bits are ignored. ...
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... These registers can be read back using one of two commands, depending on the level of accuracy required for the energy accumulator and the desire to limit the frequency of reads from the ADM1075. A bus host can read these values, and, using some difference calculations, determine the amount of energy consumed since the last read and the number of samples in that time ...
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... If the required current limit and the sense resistor is 2 mΩ, the first step is to determine the voltage coefficient. For an ADM1075-1, this is simply m = 806 × 2, giving 1612. Using Equation 1, and expressing X, in units of amps ((1612 × 10) + 20,475) × 3659 ...
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... CODE where the 12-bit ADC code. CODE V is the voltage value in volts. A LSB = 368 μV. INPUTV Rev Page Power (W)—Resistor Scaled ADM1075-1 ADM1075-2 8549 × R 4279 × R SENSE 0 0 −1 −1 = LSB × − 2048) xmV ADC /( R × 0.001) ...
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... ADM1075 ADM1075 ALERT PIN BEHAVIOR The ADM1075 provides a very flexible alert system, whereby one or more fault/warning conditions can be indicated to an external device. FAULTS AND WARNINGS A PMBus fault on the ADM1075 is always generated due to an analog event and causes a change in state in the hot swap output, turning it off. The three defined fault sources are as follows: • ...
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... The ALERTx_CONFIG command is used, as for the SMBAlert configuration, to select the specific warning threshold to be monitored. The GPO1/ ALERT1 /CONV or GPO2/ ALERT2 pin then indicates if the measured value is above or below the threshold. Rev Page ADM1075 ...
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... ASCII “ADI” 0x09 + ASCII “ADM1075-1” or “ADM1075-2” 0x01 + ASCII “1” 0x0000 0x0000 0x0000 0x01 0x8F 0x8000 0x0004 0x0000 0x00 Not applicable 0x0000 0x03000000 0x080000000000000000 ...
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... ADC codes. Description Always reads as 0000. Overvoltage threshold for the ADC_V pin measurement, expressed in ADC codes. Description Always reads as 0000. Undervoltage threshold for the ADC_V pin measurement, expressed in ADC codes. Rev Page ADM1075 Reset Access 0x0 RW 0x0 R Reset Access 0x1 ...
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... The hot swap gate drive output is disabled, and the GATE pin is pulled down. This can be due to, for example, an overcurrent fault that causes the ADM1075 to latch off, an undervoltage condition on the UVx pin, or the use of the OPERATION command to turn the output off. Always reads as 0. ...
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... An overvoltage condition on the input supply was detected by the power monitor. Latched register undervoltage condition on the input supply detected by the power monitor undervoltage condition on the input supply was detected by the power monitor. Rev Page ADM1075 Reset Access 0x0 R 0x0 R 0x0 R 0x0 ...
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... The ADM1075 has not actively limited the current into the load. 1 The ADM1075 has actively limited current into the load. This bit differs from the IOUT_OC_FAULT bit in that the HS_INLIM bit is set immediately, whereas the IOUT_OC_FAULT bit is not set unless the time limit set by the capacitor on the TIMER pin elapses ...
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... Description Input power from the VIN × IOUT calculation. Description Always reads as 0010, PMBus Specification Part I, Revision 1.2. Always reads as 0010, PMBus Specification Part II, Revision 1.2. 0000 Rev1.0. 0001 Rev1.1. 0010 Rev1.2. Rev Page ADM1075 Reset Access 0x6 R 0x0 R 0x0 R 0x0 R Reset ...
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... Always reads as 0x32 = “2” for ADM1075-2. Description Always reads as 0x01, the number of data bytes that the block read command should expect to read. Always reads as 0x31, Revision 1 of ADM1075. Description Always reads as 0000. Returns the peak IOUT current since the register was last cleared. ...
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... The power monitor also samples the voltage on the ADC_AUX pin. Always reads as 0. Reserved. Sets current sense range to 25 mV. Default for ADM1075-1. Sets current sense range to 50 mV. Default for ADM1075-2. Reserved. Disables sample averaging for current and voltage. Sets sample averaging for current and voltage to two samples. ...
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... ADM1075 ALERT1 CONFIGURATION REGISTER Address: 0xD5, Reset: 0x8000, Name: ALERT1_CONFIG Table 33. Bit Descriptions for ALERT1_CONFIG Bits Bit Name Settings 15 FET_HEALTH_BAD_EN1 14 IOUT_OC_FAULT_EN1 13 VIN_OV_FAULT_EN1 12 VIN_UV_FAULT_EN1 11 CML_ERROR_EN1 10 IOUT_OC_WARN_EN1 9 IOUT_WARN2_EN1 8 VIN_OV_WARN_EN1 7 VIN_UV_WARN_EN1 6 VAUX_OV_WARN_EN1 5 VAUX_UV_WARN_EN1 4 HS_INLIM_EN1 Description 0 Disables generation of SMBAlert when the FET_HEALTH_BAD bit is set. 1 Default. Generates SMBAlert when the FET_HEALTH_BAD bit is set ...
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... Default. Disables generation of SMBAlert when the IOUT_WARN2 bit is set. 1 Generates SMBAlert when the IOUT_WARN2 bit is set. 0 Default. Disables generation of SMBAlert when the VIN_OV_WARN bit is set. 1 Generates SMBAlert when the VIN_OV_WARN bit is set. Rev Page ADM1075 Reset Access 0x0 RW 0x0 RW 0x0 RW Reset ...
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... NACK if the command is received. This setting provides some protection against a card accidentally turning itself off 1 The OPERATION command is enabled, and the responds to it. Rev Page Data Sheet Reset Access 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x2 RW 0x0 RW Reset Access 0x0 R 0x0 RW Reset Access 0x00 R 0x0 RW ADM1075 issues a ADM1075 ...
Page 49
... Byte 4 is the low byte. This is the total number of PIN samples acquired and accumulated in the energy count accumulator. Byte 8 is the high byte, Byte 7 is the middle byte, and Byte 6 is the low byte. Rev Page ADM1075 Reset Access 0x0 RW ...
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... ADM1075 READ VAUX REGISTER Address: 0xDD, Reset: 0x0000, Name: READ_VAUX Table 40. Bit Descriptions for READ_VAUX Bits Bit Name Settings [15:12] RESERVED [11:0] READ_VAUX VAUX OV WARN LIMIT REGISTER Address: 0xDE, Reset: 0x0FFF, Name: VAUX_OV_WARN_LIMIT Table 41. Bit Descriptions for VAUX_OV_WARN_LIMIT Bits Bit Name Settings [15:12] RESERVED ...
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... OUTLINE DIMENSIONS PIN 1 0.15 0.05 COPLANARITY ORDERING GUIDE 1 Model Temperature Range ADM1075-1ARUZ −40°C to +85°C ADM1075-1ARUZ-RL7 −40°C to +85°C ADM1075-2ARUZ −40°C to +85°C ADM1075-2ARUZ-RL7 −40°C to +85°C EVAL-ADM1075EBZ RoHS Compliant Part. 2 Operating junction temperature is −40°C to +105°C. 9.80 9.70 9. 4.50 4.40 4.30 ...
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... ADM1075 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09312-0-10/11(0) Rev Page Data Sheet ...