adm1075-2aruz-rl7 Analog Devices, Inc., adm1075-2aruz-rl7 Datasheet - Page 12

• Manufacturer Part Number: adm1075-2aruz-rl7
• Description: −48 V Hot Swap Controller And Digital Power Monitor With Pmbus Interface
• Manufacturer: Analog Devices, Inc.

ADM1075
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Pin No.
Mnemonic
GPO1/
GPO2/
SDAO
SDAI
SCL
PWRGD
ADC_AUX
SPLYGD
VEE
SENSE−
SENSE+
GATE
VEE_G
ALERT1
ALERT2
/CONV
Description
General-Purpose Digital Output (GPO1).
Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or
warning conditions have been detected.
Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC
sampling cycle begins.
This pin defaults to indicate FET health mode at power-up. There is no internal pull-up on this pin.
General-Purpose Digital Output (GPO2).
Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault or
warning conditions have been detected.
This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for
further details. This pin defaults to indicate a seven-attempt fail at power-up.
There is no internal pull-up on this pin.
PMBus Serial Data Output. This is a split version of the SDA for easy use with optocouplers.
PMBus Serial Data Input. This is a split version of the SDA for easy use with optocouplers.
PMBus Clock Pin. Open-drain input requires an external resistive pull-up.
Power-Good Signal. This pin is used to indicate that the FET is no longer in the linear region and
capacitors are fully charged. See the
This pin is used to read back a voltage using the internal ADC.
This pin asserts low when the supply is within the UV and OV limits set by the UVx and OV pins.
Chip Ground Pin. Must connect to –VIN rail (lowest potential).
Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets
the analog current limit. The hot swap operation controls the external FET gate to maintain the (V
− V
Positive Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets
the analog current limit. The hot swap operation controls the external FET gate to maintain the (V
− V
Gate Output Pin. This pin is the gate drive of an external N-channel FET. It is driven by the FET drive
controller. The FET drive controller regulates to a maximum load current by regulating the GATE pin.
GATE is held low while the supply is out of the voltage range.
Chip Ground Pin. Must connect to –VIN rail (lowest potential). The PCB layout should configure this pin
as the gate pull-down return.
SENSE−
SENSE−
) sense voltage. This pin also connects to the VEE node, but should be routed separately.
) sense voltage. This pin also connects to the FET source node.
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PWRGD
section for details on assert and deassert.
Data Sheet
SENSE+
SENSE+