74vcx1632245 STMicroelectronics, 74vcx1632245 Datasheet

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74vcx1632245

Manufacturer Part Number

74vcx1632245

Description

16-bit Dual Supply Bus Transceiver Level Translator With A Side Series Resistor

Manufacturer

STMicroelectronics

Datasheet

1.74VCX1632245.pdf (18 pages)

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DESCRIPTION

The 74VCX1632245 is a dual supply low voltage

CMOS 16-BIT BUS TRANSCEIVER fabricated

with sub-micron silicon gate and five-layer metal

wiring C

interface between a 3.3V bus and a 2.5V or 1.8V

bus in a mixed 3.3V/1.8V,3.3V/2.5V and 2.5V/

1.8V supply systems, it achieves high speed

operation while maintaining the CMOS low power

dissipation.

This IC is intended for two-way asynchronous

communication between data buses and the

direction of data transmission is determined by

nDIR inputs. The enable inputs nG can be used to

disable the device so that the buses are effectively

March 2005

HIGH SPEED: t

V

LOW POWER DISSIPATION:

I

SYMMETRICAL OUTPUT IMPEDANCE:

|I

V

|I

V

BALANCED PROPAGATION DELAYS:

t

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

26Ω SERIES RESISTOR ON A SIDE OUTPUTS

OPERATING VOLTAGE RANGE:

V

Retention)

V

Retention)

MAX DATA RATES:

380 Mbps (1.8V to 3.3V translation)

260 Mbps (<1.8V to 3.3V translation)

260 Mbps (Translate to 2.5V)

210 Mbps (Translate to 1.5V)

100 Mbps (Translate to 1.2V)

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 16245

LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

CCA

PLH

OHA

OHA

CCA

CCA

CCA

CCA

CCB

≅

2

= I

| = I

| = I

(OPR) = 2.3V to 3.6V (1.2V Data

(OPR) = 1.65V to 2.7V (1.2V Data

MOS technology. Designed for use as an

= 3.0V V

= 3.0V V

= 2.3V V

LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR

t

PHL

CCB

OLA

OLA

= 20µA(MAX.) at T

= 8mA MIN at

= 18mA MIN at

CCB

CCB

CCB

PD

= 4.4ns (MAX.) at T

= 2.3V

= 1.65V or 2.3V

= 1.65V)

16-BIT DUAL SUPPLY BUS TRANSCEIVER

A

=85°C

A

=85°C

Table 1: Order Codes

isolated. The A-port interfaces with the 3V bus, the

B-port with the 2.5V and 1.8V bus.

All inputs are equipped with protection circuits

against static discharge, giving them 2KV ESD im-

munity and transient excess voltage. All floating

bus terminals during High Z State must be held

HIGH or LOW.

Figure 1: Logic Diagram

µTFBGA42

PACKAGE

TSSOP48

TFBGA54

TSSOP

n = 1, 2

74VCX1632245

TFBGA

74VCX1632245TTR

74VCX1632245LBR

74VCX1632245TBR

Rev. 14

T & R

µTFBGA

1/18

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