74VCX16827MTDX Fairchild Semiconductor, 74VCX16827MTDX Datasheet

74VCX16827MTDX

Manufacturer Part Number

74VCX16827MTDX

Description

IC BUFF DVR 20BIT LOW V 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74VCXr

Datasheet

1.74VCX16827MTD.pdf (8 pages)

Specifications of 74VCX16827MTDX

Logic Type

Buffer/Line Driver, Non-Inverting

Number Of Elements

Number Of Bits Per Element

Current - Output High, Low

12mA, 12mA

Voltage - Supply

1.4 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Logic Family

VCX

Number Of Channels Per Chip

Polarity

Non-Inverting

Supply Voltage (max)

3.6 V

Supply Voltage (min)

1.2 V

Maximum Operating Temperature

+ 85 C

Mounting Style

SMD/SMT

High Level Output Current

- 24 mA

Low Level Output Current

24 mA

Minimum Operating Temperature

- 40 C

Number Of Lines (input / Output)

20 / 3

Output Type

3-State

Propagation Delay Time

6 ns at 1.8 V, 3 ns at 2.5 V, 2.5 ns at 3.3 V

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74VCX16827MTD

74VCX16827

Low Voltage 20-Bit Buffer/Line Driver with

3.6V Tolerant Inputs and Outputs

General Description

The VCX16827 contains twenty non-inverting buffers with

3-STATE outputs to be employed as a memory and

address driver, clock driver, or bus oriented transmitter/

receiver carrying parity. The device is byte controlled. Each

byte has NOR output enables for maximum control flexibil-

ity.

The 74VCX16827 is designed for low voltage (1.2V to

3.6V) V

The 74VCX16827 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Order Number

applications with I/O capability up to 3.6V.

Package Number

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500131

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

Pin Descriptions

1.2V to 3.6V V

3.6V tolerant inputs and outputs

Power-off high impedance inputs and outputs

Supports live insertion and withdrawal (Note 1)

Static Drive (I

Uses patented noise/EMI reduction circuitry

Latch-up performance exceeds 300 mA

ESD performance:

Pin Names

2.5 ns max for 3.0V to 3.6V V

Human body model

Machine model

–I

24 mA @ 3.0V V

–O

Package Description

Output Enable Input (Active LOW)

Inputs

Outputs

supply operation

)

200V

2000V

through a pull-up resistor; the minimum

March 1998

Revised October 2002

Description

www.fairchildsemi.com

Related parts for 74VCX16827MTDX

74VCX16827MTDX Summary of contents

Page 1

... MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2002 Fairchild Semiconductor Corporation Features 1.2V to 3.6V V supply operation CC 3 ...

Page 2

Connection Diagram www.fairchildsemi.com Truth Tables Inputs – Inputs – ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 3) 0. Input Diode Current ( Output ...

Page 4

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power-OFF Leakage Current OFF I Quiescent Supply Current CC I Increase in I per Input CC CC Note ...

Page 5

AC Electrical Characteristics Symbol Parameter t , Propagation Delay C PHL t PLH Output Enable Time C PZL t PZH Output Disable Time C PLZ t PHZ C t Output to Output Skew C ...

Page 6

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low ...

Page 7

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 6. Waveform for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output High Enable and Disable Times for Low ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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