74vcxh16244g Fairchild Semiconductor, 74vcxh16244g Datasheet

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74vcxh16244g

Manufacturer Part Number
74vcxh16244g
Description
74vcxh16244 Low Voltage 16-bit Buffer/line Driver With Bushold
Manufacturer
Fairchild Semiconductor
Datasheet
© 2005 Fairchild Semiconductor Corporation
74VCXH16244G
(Note 1)(Note 2)
74VCXH16244MTD
(Note 2)
74VCXH16244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
General Description
The VCXH16244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The VCXH16244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74VCXH16244 is designed for low voltage (1.2V to
3.6V) V
The 74VCXH16244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Note 1: Ordering Code “G” indicates Tray.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with output capability up to 3.6V.
Package Number
(Preliminary)
BGA54A
MTD48
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500230
Features
1.2V to 3.6V V
3.6V tolerant control inputs and outputs
Bushold on data inputs eliminating the need for external
pull-up/pull-down resistors
t
Static Drive (I
Uses patented noise/EMI reduction circuitry
Latch-up performance exceeds 300 mA
ESD performance:
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
PD
2.5 ns max for 3.0V to 3.6V V
r
Human body model
Machine model
24 mA @ 3.0V V
Package Description
OH
CC
/I
OL
supply operation
!
)
200V
CC
!
2000V
November 1999
Revised June 2005
CC
www.fairchildsemi.com

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74vcxh16244g Summary of contents

Page 1

... The 74VCXH16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation. Ordering Code: Order Number Package Number 74VCXH16244G BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) (Preliminary) 74VCXH16244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6 ...

Page 2

Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW –I Bushold Inputs –O Outputs Connect ...

Page 3

Functional Description The 74VCXH16244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) con- trolled with each nibble functioning identically, but indepen- dent of each other. The control pins may be shorted together to obtain full ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED  Outputs Active (Note 4) 0. Input Diode Current ( ...

Page 5

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current Control Pins I Data Pins I Bushold Input Minimum I(HOLD) Drive Hold Current I Bushold Input Over-Drive I(OD) Current to Change State I 3-STATE Output ...

Page 6

AC Electrical Characteristics Symbol Parameter t Propagation Delay C PHL t PLH C t Output Enable Time C PZL t PZH C t Output Disable Time C PLZ t PHZ C t Output to Output Skew C OSHL t (Note ...

Page 7

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low ...

Page 8

AC Loading and Waveforms (V t PLH t PZL t PZH FIGURE 6. Waveform for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 8. 3-STATE Output Low Enable and Disable ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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