74vcxh162373 Fairchild Semiconductor, 74vcxh162373 Datasheet

74vcxh162373

Manufacturer Part Number

74vcxh162373

Description

74vcxh162373 Low Voltage 16-bit Transparent Latch With Bushold And 26w Series Resistors In Outputs

Manufacturer

Fairchild Semiconductor

Datasheet

1.74VCXH162373.pdf (9 pages)

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Euro Chip Distribution

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74vcxh162373MTX

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74VCXH162373MTD

74VCXH162373MTX

(Note 1)

74VCXH162373

Low Voltage 16-Bit Transparent Latch with Bushold

and 26: Series Resistors in Outputs

General Description

The VCXH162373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch enable

(LE) is HIGH. When LE is LOW, the data that meets the

setup time is latched. Data appears on the bus when the

Output Enable (OE) is LOW. When OE is HIGH, the out-

puts are in a high impedance state.

The VCXH162373 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level.

The VCXH162373 is also designed with 26

tors in the outputs. This design reduces line noise in appli-

cations such as memory address driver, clock drivers and

bus transceivers/transmitters.

The 74VCXH162373 is designed for low voltage (1.4V to

3.6V) V

The 74VCXH162373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Note 1: Use this Order Number to receive devices in Tape and Reel.

Logic Symbol

Ordering Number

applications with output compatibility up to 3.6V.

Package

Number

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TUBES]

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TAPE and REEL]

series resis-

DS500227

Features

Pin Descriptions

1.4V to 3.6V V

3.6V tolerant control inputs and outputs

Bushold on data inputs eliminates the need for external

pull-up/pull-down resistors

Static Drive (I

Uses patented noise/EMI reduction circuitry

Latch-up performance exceeds 300 mA

ESD performance:

Pin Names

3.3 ns max for 3.0V to 3.6V V

Human body model

Machine model

12 mA @ 3.0V V

series resistors in outputs

Package Description

–I

–O

to O

)

Output Enable Input (Active LOW)

Latch Enable Input

Bushold Inputs

Outputs

supply operation

)

200V

2000V

January 2000

Revised June 2005

Description

www.fairchildsemi.com

Related parts for 74vcxh162373

74vcxh162373 Summary of contents

Page 1

... The VCXH162373 is also designed with 26 tors in the outputs. This design reduces line noise in appli- cations such as memory address driver, clock drivers and bus transceivers/transmitters. The 74VCXH162373 is designed for low voltage (1.4V to 3.6V) V applications with output compatibility up to 3.6V. CC The 74VCXH162373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation ...

Page 2

... Connection Diagram Functional Description The 74VCXH162373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 3) 0. Input Diode Current ( ...

Page 4

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current Control Pins I Data Pins I Bushold Input Minimum I(HOLD) Drive Hold Current I Bushold Input Over-Drive I(OD) Current to Change State I 3-STATE Output ...

Page 5

AC Electrical Characteristics Symbol Parameter t Propagation Delay C PHL PLH Propagation Delay C PHL PLH Output Enable Time C PZL t PZH C t ...

Page 6

Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP OL V Quiet Output Dynamic Valley V OLV OL V Quiet Output Dynamic Valley V OHV OH Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT ...

Page 7

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low ...

Page 8

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 8. Waveform for Inverting and Non-Inverting Functions FIGURE 9. 3-STATE Output HIGH Enable and Disable Times for Low ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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