74vcxf162835 ETC-unknow, 74vcxf162835 Datasheet

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74vcxf162835

Manufacturer Part Number
74vcxf162835
Description
Low Voltage 18-bit Universal Bus Driver With 3.6v Tolerant Outputs And 26? Series Resistors In Outputs
Manufacturer
ETC-unknow
Datasheet
© 2000 Fairchild Semiconductor Corporation
74VCXF162835MTD
74VCXF162835MTX
(Note 1)
74VCXF162835
Low Voltage 18-Bit Universal Bus Driver with 3.6V
Tolerant Outputs and 26
General Description
The VCXF162835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (I
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The VCXF162835 is designed with 26
the outputs. This design reduces noise in applications such
as memory address drivers, clock drivers, and bus trans-
ceivers/transmitters.
The 74VCXF162835 is designed for low voltage (1.65V to
3.6V) V
The 74VCXF162835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Note 1: Use this Order Number to receive devices in Tape and Reel.
Order Number
CC
applications with I/O capability up to 3.6V.
Package
Number
MTD56
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
n
) to Outputs (O
series resistors in
DS500259
n
) on
Series Resistors in Outputs
Features
Compatible with PC133 DIMM module specifications
1.65V–3.6V V
3.6V tolerant outputs
26 series resistors in outputs
t
Power-down high impedance outputs
Static Drive (I
Latchup performance exceeds 300 mA
ESD performance:
PD
Package Description
3.2 ns max for 3.0V to 3.6V V
4.1 ns max for 2.3V to 2.7V V
7.4 ns max for 1.65V to 1.95V V
Human body model
Machine model 200V
12 mA @ 3.0V V
8 mA @ 2.3V V
3 mA @ 1.65V V
(CLK to O
OH
n
CC
)
/I
specifications provided
OL
)
CC
CC
CC
2000V
October 1999
Revised November 2000
CC
CC
CC
www.fairchildsemi.com

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74vcxf162835 Summary of contents

Page 1

... The VCXF162835 is designed with 26 series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus trans- ceivers/transmitters. The 74VCXF162835 is designed for low voltage (1.65V to 3.6V) V applications with I/O capability up to 3.6V. CC The 74VCXF162835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation ...

Page 2

Connection Diagram Logic Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) LE Latch Enable Input CLK Clock Input Data Inputs 3-STATE Outputs 1 18 Truth Table Inputs ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 5) 0. Input Diode Current ( 0.5V ...

Page 4

DC Electrical Characteristics (2.3V Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ ...

Page 5

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX Propagation Delay PHL PLH Bus to Bus Propagation Delay PHL PLH Clock to Bus Propagation Delay PHL PLH LE to Bus ...

Page 6

Capacitance Symbol Parameter C Input Capacitance IN C Input/Output Capacitance I/O C Power Dissipation Capacitance Characteristics OUT OUT FIGURE 1. Characteristics for Output - Pull Up Drive FIGURE 2. Characteristics for Output - Pull Down Driver ...

Page 7

AC Loading and Waveforms TEST PLH PHL PZL PLZ PZH PHZ FIGURE 4. Waveform for Inverting and Non-inverting Functions t t 2.0ns, 10 FIGURE 6. 3-STATE Output ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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