stm706r STMicroelectronics, stm706r Datasheet - Page 9

• Manufacturer Part Number: stm706r
• Description: 3v Supervisor
• Manufacturer: STMicroelectronics

OPERATION
Reset Output
The STM70x Supervisor asserts a reset signal to
the MCU whenever V
threshold (V
WDO is connected to MR), or when the Push-but-
ton Reset Input (MR) is taken low. RST is guaran-
teed to be a logic low (logic high for STM706P and
STM708T/S/R) for V
for T
During power-up, once V
threshold an internal timer keeps RST low for the
reset time-out period, t
returns high.
If V
low. Each time RST is asserted, it stays low for at
least the reset time-out period (t
goes below the reset threshold the internal timer
clears. The reset timer starts when V
above the reset threshold.
Push-button Reset Input
A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for t
29., page
has an internal 40k
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open mo-
mentary switch from MR to GND to create a man-
ual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide ad-
ditional noise immunity. MR may float, or be tied to
V
Watchdog Input (STM706T/S/R and STM706P)
The watchdog timer can be used to detect an out-
of-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within t
Watchdog Output pin (WDO) is asserted. The in-
ternal 1.6sec timer is cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
See
STM706P.
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is re-
leased, the timer starts counting.
CC
CC
which can detect pulses as short as 50ns.
A
when not used.
Figure 30., page 19
= 0° C to 85° C.
drops below the reset threshold, RST goes
19) after it returns high. The MR input
RST
), a watchdog time-out occurs (if
CC
pull-up resistor, allowing it to
CC
rec
< V
. After this interval RST
for STM706T/S/R and
CC
goes below the reset
RST
exceeds the reset
rec
down to V
WD
). Any time V
rec
(1.6sec), the
(see
CC
CC
returns
Figure
=1V
CC
Watchdog Output (STM706T/S/R and
STM706P)
When V
will go low even if the watchdog timer has not yet
timed out. However, unlike the reset output, WDO
goes high as soon as V
threshold. WDO may be used to generate a reset
pulse by connecting it to the MR input.
Power-fail Input/Output
The Power-fail Input (PFI) is compared to an inter-
nal reference voltage (independent from the V
comparator). If PFI is less than the power-fail
threshold (V
go low. This function is intended for use as an un-
dervoltage detector to signal a failing power sup-
ply. Typically PFI is connected through an external
voltage divider (see
the unregulated DC input (if it is available) or the
regulated output of the V
divider can be set up such that the voltage at PFI
falls below V
regulated V
processor drops below the minimum operating
voltage.
If the comparator is unused, PFI should be con-
nected to V
may be connected to MR on the STM70x so that a
low voltage on PFI will generate a reset output.
Ensuring a Valid Reset Output Down to
V
When V
put can no longer be guaranteed, and becomes
essentially an open circuit. If a high value pull-
down resistor is added to the RST pin, the output
will be held low during this condition. A resistor val-
ue of approximately 100k will be large enough to
not load the output under operating conditions, but
still sufficient to pull RST to ground during this low
voltage condition (see Figure 11).
Figure 11. Reset Output Valid to Ground
Circuit
CC
STM706T/S/R; STM706P; STM708T/S/R
= 0V
CC
CC
falls below 1V, the state of the RST out-
drops below the reset threshold, WDO
CC
PFI
SS
PFI
), the Power-Fail Output (PFO) will
input to the STM70x or the micro-
STM70x
and PFO left unconnected. PFO
several milliseconds before the
RST
Figure 10., page
CC
CC
regulator. The voltage
exceeds the reset
AI08844
R1
8) to either
9/26
RST