ptn3392 NXP Semiconductors, ptn3392 Datasheet - Page 12

• Manufacturer Part Number: ptn3392
• Description: 2-lane Displayport To Vga Adapter Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PTN3392
Product data sheet
7.4.1 S0 = logic 0
7.4.2 S0 = logic 1
7.5 EDID handling
If S0 is left open-circuit (internal pull-down) (DisplayPort v1.1a compliant behavior),
PTN3392 behaves as stated in VESA DisplayPort v1.1a, sections 7 and 8. PTN3392 will
keep HPD LOW during its internal initialization sequence after power-up. It will then
update DPCD register SINK_COUNT to the expected value, depending if a VGA monitor
is detected or not, and will then assert HPD HIGH whatever is the value of SINK_COUNT
register. Each time PTN3392 detects a change in the VGA monitor connection status, it
will update the SINK_COUNT register accordingly, set
DOWNSTREAM_PORT_STATUS_CHANGED register bit to 1 and generate IRQ_HPD
pulse to signal the source about the status change. Refer to
flowchart.
If S1 is tied to HIGH with external pull-up (best interoperability behavior), the PTN3392 will
keep HPD LOW during its internal initialization sequence after power-up. It will then wait
for a VGA monitor to be connected downstream before asserting HPD HIGH to force
source waiting for a VGA monitor before starting protocol negotiations. If a VGA monitor is
disconnected during normal operations, PTN3392 will assert HPD LOW so that the source
will consider that no sink device is connected anymore. Refer to
flowchart.
Figure 4
DisplayPort source and a VGA monitor. The PTN3392 converts a DP I
request to I
the DP source via an I
It is the responsibility of the source to only choose video modes which are declared in the
EDID and to adjust the DisplayPort link capabilities (link rate and lane count) to provide
the necessary video bandwidth. The PTN3392 does not cache or modify the EDID to
match the capabilities of the DisplayPort link data.
If the DisplayPort source drives display modes that are not specified in the EDID mode
list, the PTN3392 will not detect such conditions, and will display at its output what it is
presented by the DisplayPort source.
Fig 4.
source device
shows a DisplayPort-to-analog video converter (or dongle) situated between the
DisplayPort to VGA adapter IC (dongle) sits between the DisplayPort source and a
VGA monitor with EDID
DP Tx
2
C on the monitor's DDC bus. The monitor's EDID read data is then returned to
All information provided in this document is subject to legal disclaimers.
DisplayPort
box-to-box
2
C Over AUX response issued by the PTN3392.
Rev. 2 — 15 July 2010
DisplayPort to VGA adapter IC
with DPCD
DP Rx
VIDEO DAC
2-lane DisplayPort to VGA adapter IC
box-to-box
legacy
Figure
Figure
3, S0 = LOW
VGA DISPLAY
WITH EDID
sink device
2
PTN3392
© NXP B.V. 2010. All rights reserved.
C Over AUX
3, S0 = HIGH
002aae039
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