sta335bwqs STMicroelectronics, sta335bwqs Datasheet

Page 1

... Field proven stereo soundfield – Provides improved audio image width, – Synthesizes a 3-D stereo soundfield PowerSSO-36 slug down package. Package PowerSSO-36 slug down PowerSSO-36 slug down Rev 3 STA335BWQS with QSound QHD PowerSSO-36 slug down 2 S input data interface ® enhancement technology ...

Page 2

... Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 5.1.2 5.2 Serial audio interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.1 6.1.2 6.1.3 6.1.4 6.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/72 ® ® QHD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STA335BWQS ...

Page 3

... STA335BWQS 6.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3.1 6.3.2 6.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 Configuration register A (addr 0x00 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.2 Configuration register B (addr 0x01 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 Configuration register C (addr 0x02 7.3.1 7.3.2 7.3.3 7.4 Configuration register D (addr 0x03 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write mode sequence ...

Page 4

... Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 AutoModes™ register 1 (0x0B AutoModes™ register 2 (0x0C interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STA335BWQS ...

Page 5

... STA335BWQS 7.10 Tone control register (addr 0x11 7.10.1 7.11 Dynamics control registers (addr 0x12 to 0x15 7.11.1 7.11.2 7.11.3 7.11.4 7.12 User-defined coefficient control registers (addr 0x16 to 0x26 7.12.1 7.12.2 7.12.3 7.12.4 7.12.5 7.12.6 7.12.7 7.12.8 7.12.9 7.12.10 Coefficient a1 data register bits 7 7.12.11 Coefficient a2 data register bits 23: 7.12.12 Coefficient a2 data register bits 15 7.12.13 Coefficient a2 data register bits 7 7.12.14 Coefficient b0 data register bits 23: 7.12.15 Coefficient b0 data register bits 15 ...

Page 6

... Contents 8.2 PLL filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11 License information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 70 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6/72 STA335BWQS ...

Page 7

... STA335BWQS List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Thermal data Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 9. Register summary Table 10. MCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. ...

Page 8

... Release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 64. LnAT bits, anti-clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 65. LnRT bits, anti-clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 66. LnAT bits, dynamic range compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 67. LnRT bits, dynamic range compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 68. RAM block for biquads, mixing, scaling and bass setup Table 69. PowerSSO-36 slug down dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 70. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8/72 STA335BWQS ...

Page 9

... Figure 2. Pin connection PowerSSO-36 (top view Figure 3. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4. Power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. Test circuit Figure 6. Test circuit Figure 7. STA335BWQS processing data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 Figure Figure 9. Left justified Figure 10. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 11. Read mode sequence Figure 12. ...

Page 10

... DDX power-output stage and QSound QHD single-chip DDX solution comprising high-quality, high-efficiency and all digital amplification. The STA335BWQS is part of the Sound Terminal™ family that provides full digital audio streaming to the speaker offering cost effectiveness, low energy dissipation and sound enrichment. ...

Page 11

... STA335BWQS 1.2 Block diagram Figure 1. Block diagram interface Volume control PLL Digital signal processing Protection current/thermal Power control DDX Regulators Channel 1A Channel 1B Logic Channel 2A Channel 2B Bias Power Description 11/72 ...

Page 12

... VCC1 11 GND1 12 OUT1A 13 14 VDD 15 CONFIG Type Name GND GND_SUB TEST_MODE I/O VSS I/O VCC_REG O OUT2B GND GND2 Power VCC2 O OUT2A O OUT1B STA335BWQS 36 VDD_DIG 35 GND_DIG 34 SCL 33 SDA 32 INT_LINE 31 RESET 30 SDI 29 LRCKI 28 BICKI 27 XTI 26 PLL_GND 25 FILTER_PLL VDD_PLL 24 PWRDN 23 GND_DIG 22 VDD_DIG 21 20 TWARN/OUT4A ...

Page 13

... STA335BWQS Table 2. Pin description (continued) Pin Type Name Power VCC1 GND GND1 I/O OUT1A GND GND_REG Power VDD I CONFIG O OUT3B/DDX3B O OUT3A/DDX3A O EAPD/OUT4B I TWARN/OUT4A Power VDD_DIG GND GND_DIG I PWRDN Power ...

Page 14

... T Thermal shut-down junction temperature th-sdj T Thermal warning temperature th-w T Thermal shut-down hysteresis th-sdh R Thermal resistance junction-ambient th j-amb 1. See Section 9: Package thermal characteristics on page 66 14/72 Parameter Min 140 18 (1) for details. STA335BWQS Typ Max Unit 1.5 °C/W 150 160 °C 130 ° °C ...

Page 15

... STA335BWQS 3 Electrical specifications 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol V Power supply voltage (VCC1, VCC2) cc VDD_DIG Digital supply voltage VDD_PLL PLL supply voltage T Operating junction temperature op T Storage temperature stg Note: Stresses beyond those listed under “Absolute maximum ratings” make cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “ ...

Page 16

... THD = 1% VCC = 24 V THD = 10% THD = 1% VCC = 24 V THD = 10% THD = 1% Ω THD = STA335BWQS Min Typ Max 10 10 0.2* VDD_DIG VDD_DIG 0.4* VDD_DIG VDD_DIG 66 125 50 Min Typ Max Unit 6.6 8 200 280 mΩ ...

Page 17

... STA335BWQS Table 7. Electrical specifications - power section (continued) Symbol Parameter Power Pchannel/Nchannel Idss leakage I Low current dead time (static) LDT High current dead time I HDT (dynamic) t Rise time r t Fall time f Supply voltage operating V cc voltage Supply current from Vcc in power down ...

Page 18

... TC TC Don’t care Don’t care Don’t care Don’t care Don’t care 2 C program, sequence start Don’t care Don’t care STA335BWQS CMD0 CMD0 CMD0 CMD0 CMD0 CMD1 CMD1 CMD1 CMD1 CMD1 CMD2 CMD2 ...

Page 19

... STA335BWQS 3.6 Testing Figure 5. Test circuit 1 Duty cycle = 50% Figure 6. Test circuit 2 Duty cycle=A M58 DTin(A) INA M57 Low current dead time = MAX(DTr, DTf) +Vcc M58 OUTxY INxY M57 gnd High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B DTout(A) Q1 Rload=4Ω ...

Page 20

... Processing data paths 4 Processing data paths Here are some diagrams that represent the data processing paths inside STA335BWQS. A 2-times oversampling FIR filter allows audio processing. Then a selectable high-pass filter removes the DC level. Four biquad filters allow a full equalization system. A final crossover filter is present ...

Page 21

... EAPD 19 5.1.1 Power-down function Pin PWRDN (23) is used to power down the STA335BWQS. PWRDN = 0 (GND) → Power down PWRND = 1 (VDD) → Normal operation During the power-down sequence the output begins a gradual (soft) mute. After the mute condition is reached the power stage is switched off (Hi-Z) then the master clock to all internal hardware blocks is gated ...

Page 22

... Serial audio interface protocols The STA335BWQS serial audio input interfaces with standard digital audio components and accepts serial data formats. The STA335BWQS always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 29), serial clock BICKI (pin 28) and serial data SDI (pin 30) ...

Page 23

... SA port configuration, 0x38 when and 0x3A when The eighth bit (LSB) identifies read or write operation RW, this bit is set read mode and 0 for write mode. After a START condition the STA335BWQS identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time ...

Page 24

... After receiving, the internal byte address the STA335BWQS again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA335BWQS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition ...

Page 25

... STA335BWQS 6.4.5 Write mode sequence Figure 10. Write mode sequence BYTE DEV-ADDR WRITE START MULTIBYTE DEV-ADDR WRITE START 6.4.6 Read mode sequence Figure 11. Read mode sequence ACK CURRENT DEV-ADDR ADDRESS READ START RW ACK RANDOM DEV-ADDR ADDRESS READ START RW RW= ACK HIGH SEQUENTIAL DEV-ADDR CURRENT ...

Page 26

... C1B22 C1B21 C1B20 C1B14 C1B13 C1B12 C1B6 C1B5 C1B4 C2B22 C2B21 C2B20 C2B14 C2B13 C2B12 C2B6 C2B5 C2B4 C3B22 C3B21 C3B20 STA335BWQS IR0 MCS2 MCS1 SAI3 SAI2 SAI1 CSZ1 CSZ0 OM1 PSL DSPB DEMP AME NSBW MPC BCLE IDE OCFG1 ...

Page 27

... STA335BWQS Table 9. Register summary (continued) Addr Name D7 0x1E A1cf2 C3B15 0x1F A1cf3 C3B7 0x20 A2cf1 C4B23 0x21 A2cf2 C4B15 0x22 A2cf3 C4B7 0x23 B0cf1 C5B23 0x24 B0cf2 C5B15 0x25 B0cf3 C5B7 0x26 Cfud Reserved Reserved Reserved 0x27 MPCC1 MPCC15 MPCC14 0x28 ...

Page 28

... Register description The STA335BWQS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is: 32.768 MHz for 32 kHz 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz ...

Page 29

... R The on-chip STA335BWQS power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the 3-state output (setting which directs the power output block to begin recovery), holds for period of time in the range of 0 ...

Page 30

... Serial data interface The STA335BWQS audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA335BWQS always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12 ...

Page 31

... STA335BWQS Table 19. Support serial audio input formats for MSB-first (SAIFB = 0) BICKI 32fs 48fs 64fs Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1) BICKI 32fs 48fs SAI [3:0] SAIFB 2 0000 15-bit data 0001 0 Left/right-justified 16-bit data 2 0000 23-bit data ...

Page 32

... C1IM 1: Processing channel 1 receives Right I 0: Processing channel 2 receives Left I 1 C2IM 1: Processing channel 2 receives Right can be mapped to any internal processing channel via the 2 S input channel to its corresponding processing channel. STA335BWQS Interface Format 24-bit data 20-bit data 2 I ...

Page 33

... STA335BWQS 7.3 Configuration register C (addr 0x02 OCRB Reserved 1 0 ® 7.3.1 DDX power output mode Table 23. OM Bit R The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. Table 24. Output modes ...

Page 34

... Table 28. HPB Bit R The STA335BWQS features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. When HPB = 0, this filter is enabled. 7.4.2 De-emphasis Table 29. ...

Page 35

... STA335BWQS Setting the DSPB bit bypasses the EQ function of the STA335BWQS. 7.4.4 Post-scale link Table 31. PSL Bit R Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster. ...

Page 36

... Use standard MPC coefficient 0 MPCV 1: Use MPCC bits for MPC coefficient RST Name Setting of 1 enables Power Bridge correction for 1 MPC THD reduction near maximum power output. Name 1: Third-order NS 0 NSBW 0: Fourth-order NS STA335BWQS Description AME NSBW MPC Description Description Description D0 ...

Page 37

... RST 3 RW STA335BWQS features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~ this mode, which is still greater than the SNR of AM radio. ...

Page 38

... D5 D4 ECLE LDTE 0 1 RST Name 0 OCFG0 Selects the output configuration 0 OCFG1 Output configuration Binary 0 ° Binary 90° Binary 0° Binary 90° w/ C3BO 45° w/ C3BO 45° STA335BWQS BCLE IDE OCFG1 Description Config pin D0 OCFG0 ...

Page 39

... Power Device EAPD STA335BWQS can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. The PWM slot always has a time duration fs) seconds and defines the maximum extension for PWM rising and falling edges, that is, rising edge as far as the falling edge cannot range outside PWM slot boundaries. ...

Page 40

... In this configuration, no volume control or EQ have effect on channel 3 and 4. Figure 17 shows the PWM slot phases for this configuration. Figure 17. 2.0 channels (OCFG = 00) PWM slots. 40/72 OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B STA335BWQS ...

Page 41

... STA335BWQS 2.1 channels, two half bridges + one full bridge (OCFG = 01) DDX1A : OUT1A DDX2A : OUT1B DDX3A : OUT2A DDX3B : OUT2B DDX1A : OUT3A DDX1B : OUT3B DDX2A : OUT4A DDX2B : OUT4B DDX1A/1B configured as binary DDX2A/2B configured as binary DDX3A/3B configured as binary DDX4A/4B not used. In this configuration, channel 3 has full control (for example, on volume, EQ). On OUT3/OUT4 channels the channel 1 and channel 2 PWM are replicated ...

Page 42

... Setting the IDE bit enables this function, which looks at the input I automatically mute if the signals are perceived as invalid. 42/72 OUT1A OUT1A OUT1B OUT1B OUT2A OUT2A OUT2B OUT2B OUT3A OUT3A OUT3B OUT3B RST Name Setting of 1 enables the automatic invalid input 1 IDE detect mute STA335BWQS Description 2 S data and will ...

Page 43

... STA335BWQS 7.6.3 Binary output mode clock loss detection Table 47. BCLE Bit R Detects loss of input MCLK in binary mode and will output 50% duty cycle. 7.6.4 LRCK double trigger protection Table 48. LDTE Bit R Actively prevents double trigger of LRCLK. 7.6.5 Auto EAPD on clock loss Table 49. ...

Page 44

... Line output variable - CH3 volume effects line output Line output variable with EQ - CH3 volume effects line output D5 D4 MV5 MV4 C1V5 C1V4 C2V5 C2V4 1 0 STA335BWQS C3M C2M C1M MV3 MV2 MV1 ...

Page 45

... C3V6 0 1 The volume structure of the STA335BWQS consists of separate volume registers for each channel and a master volume register to provide an offset to each channel volume setting. The individual channel volumes are adjustable in 0.5 dB steps from + -80 dB example if C3V = 0x00 (+48 dB) and MV = 0x18 (-12 dB) then the total gain for channel 3 = +36 dB ...

Page 46

... Hard channel mute Hard channel mute AMGC1 AMGC2 Reserved User programmable clipping 2.1 AC limited clipping (10%) 2.1 DRC nighttime listening mode 2 XO1 XO0 AMAM2 STA335BWQS Volume … -59.5 dB -60 dB -61 dB -62 dB … -80 dB … Reserved Reserved Reserved Mode AMAM1 ...

Page 47

... STA335BWQS 7.8.3 AM interference frequency switching Table 56. AM enable Bit R Table 57. AutoModes™ AM switching frequency selection AMAM[2:0] 000 001 010 011 100 101 110 7.8.4 Bass management crossover Bit R Table 58. Bass management crossover frequency XO[3:0] 0000 0001 0010 0011 0100 ...

Page 48

... Hz 300 Hz 320 Hz 340 Hz 360 C1LS1 C1LS0 C1BO C2LS1 C2LS0 C2BO C3LS1 C3LS0 C3BO STA335BWQS C1VPB C1EQBP C1TCB C2VPB C2EQBP C2TCB C3VPB Reserved Reserved ...

Page 49

... STA335BWQS 7.9.4 Binary output enable registers Each individual channel output can be set to output a binary PWM stream. In this mode output channel is considered the positive output and output B is negative inverse. CnBO: 0: DDX 3-state output - normal operation 1: Binary output 7.9.5 Limiter select Limiter selection can be made on a per-channel basis according to the channel limiter select bits ...

Page 50

... L1A1 L1A0 L1R3 L1AT1 L1AT0 L1RT3 L2A1 L2A0 L2R3 STA335BWQS BTC2 BTC1 BTC0 L1R2 L1R1 L1R0 L1RT2 L1RT1 L1RT0 ...

Page 51

... The limiter attack thresholds are determined by the LnAT registers recommended in anti-clipping mode to set this to 0 dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within STA335BWQS it is possible to exceed 0 dBFS or any other LnAT setting, when this occurs, the limiter, when active, automatically starts reducing the gain ...

Page 52

... LnR[3:0] 3.904 (fast) 3.859 3.859 3.849 3.793 3.750 3.682 3.549 3.483 3.448 3.357 3.284 3.082 2.957 2.864 2.864 (slow) STA335BWQS Attack rate (dB/ms) Release rate (dB/s) ...

Page 53

... STA335BWQS Table 64. LnAT bits, anti-clipping 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 65. LnRT bits, 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 LnAT[3:0] -12 - ...

Page 54

... LnRT[3: LnAT[3:0] -31 -29 -27 -25 -23 -21 -19 -17 -16 -15 -14 -13 -12 - LnRT[3:0] -∞ -38 dB -36 dB -33 dB -31 dB -30 dB -28 dB -26 dB -24 dB -22 dB STA335BWQS Anti-clipping (AC) (dB relative to FS) Dynamic range compression (DRC) (dB relative to volume) Dynamic range compression (DRC) (dB relative to volume + LnAT) ...

Page 55

... STA335BWQS Table 67. LnRT bits, dynamic range compression 1010 1011 1100 1101 1110 1111 7.12 User-defined coefficient control registers (addr 0x16 to 0x26) 7.12.1 Coefficient address register D7 D6 Reserved Reserved 0 7.12.2 Coefficient b1 data register bits 23: C1B23 C1B22 0 0 7.12.3 Coefficient b1 data register bits 15 C1B15 C1B14 0 7 ...

Page 56

... D5 D4 C3B21 C3B20 C3B13 C3B12 C3B5 C3B4 C4B21 C4B20 C4B13 C4B12 0 0 STA335BWQS C2B11 C2B10 C2B9 C2B3 C2B2 C2B1 C3B19 C3B18 C3B17 C3B11 ...

Page 57

... Reserved Reserved 0 Coefficients for user-defined EQ, Mixing, Scaling, and Bass Management are handled internally in the STA335BWQS via RAM. Access to this RAM is available to the user via register interface. A collection of I contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM ...

Page 58

... C address 0x1D address 0x1E address 0x1F address 0x20 address 0x21 address 0x22 address 0x23 address 0x24 address 0x25 register 0x16 address 0x17 address 0x18 address 0x19 address 0x26. STA335BWQS ...

Page 59

... STA335BWQS generates the RAM addresses as offsets from this base value to write the complete set of coefficient data. 7.12.18 User-defined EQ The STA335BWQS provides the ability to specify four EQ filters (biquads) per each of the two input channels. The biquads use the following equation: Y[n] = 2(b /2)X[n] + 2(b 0 ...

Page 60

... Pre-scale The STA335BWQS provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I and the bass-management ...

Page 61

... STA335BWQS Table 68. RAM block for biquads, mixing, scaling and bass setup (continued) Index (decimal) Index (hex) 5 … … 0x05 Channel 1 - Biquad 2 … … 0x13 Channel 1 - Biquad 4 0x14 Channel 2 - Biquad 1 0x15 … ...

Page 62

... DCC11 DCC5 DCC4 DCC3 FDRC13 FDRC12 FDRC11 FDRC5 FDRC4 FDRC3 STA335BWQS MPCC10 MPCC9 MPCC8 MPCC2 MPCC1 MPCC0 DCC10 DCC9 DCC8 DCC2 ...

Page 63

... STA335BWQS 7.16 Device status register (addr 0x2D PLLUL FAULT This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked. ...

Page 64

... Application and power supplies Figure 21 below shows the circuit diagram of a typical application for STA335BWQS. Particular care has to be given to the layout of the PCB, especially the power supplies. The 3.3-Ω resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This helps to prevent unwanted oscillation on the digital portion of the device due to inductive tracks of the PCB ...

Page 65

... STA335BWQS 8.3 Typical output configuration Figure 23 shows the typical output configuration used for BTL stereo mode. Please refer to the application note for other recommended output configuration schematics. Figure 23. Output configuration for stereo BTL mode OUT1A OUT1A OUT1A OUT1B OUT1B OUT1B OUT2A OUT2A ...

Page 66

... The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. The max estimated dissipated power for the STA335BWQS is Ω Ω, 8 Ω Ω Figure 24 ...

Page 67

... STA335BWQS 10 Package information Figure 26 shows the package outline and Figure 26. PowerSSO-36 slug down outline drawing Package information Table 69 gives the dimensions. 67/72 ...

Page 68

... STA335BWQS inch Min Typ Max - 0.097 - 0.094 - 0.004 - 0.014 - 0.013 - 0.413 - 0.299 0.020 0.335 0.091 - 0.004 0.413 0.016 8 degrees 0.039 0.169 10 degrees 0.047 0.031 0.114 0.144 0.039 0.185 0.280 ® ...

Page 69

... QXpander , QHD ® QHD and QXpander obtained with the STA335BWQS via STMicroelectronics, please contact the HPC Audio Division Product Manager for details. Alternatively the license can be obtained directly from QSound Labs Inc. For details please contact: sales@qsound.com or QSound Labs, Inc ...

Page 70

... Trademarks and other acknowledgements 12 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. AutoModes is a trademark of Apogee Technology Inc SoundTerminal is a trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. QHD and QXpander are registered trademarks of QSound Labs Inc. 70/72 STA335BWQS ...

Page 71

... STA335BWQS 13 Revision history Table 70. Document revision history Date 26-Mar-2008 15-May-2008 12-Aug-2010 Revision 1 Initial release Updated pins 19 and 20 names (4A->4B, 4B->4A) in page 12 Added power-off sequence, 2 Added Chapter 5 on page 21 description) Updated release rate values in Updated package information in 3 Removed erroneous watermark Revision history Changes ...

Page 72

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 72/72 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STA335BWQS ...