sta381bw STMicroelectronics, sta381bw Datasheet - Page 66

• Manufacturer Part Number: sta381bw
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

Register description: New Map
6.18.3
6.18.4
6.18.5
6.18.6
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LRCK double trigger protection
Table 50.
Actively prevents double triggering of LRCLK.
Auto EAPD on clock loss
Table 51.
When active, issues a power device power-down signal (EAPD) on clock loss detection.
Power-down
Table 52.
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power-stage, then the master clock to all internal hardware except the
I
state is preserved once the device recovers from power down.
External amplifier power-down
Table 53.
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed on a low-power state (disabled). This
register also controls the FFX4B/EAPD output pin when OCFG = 11.
2
C block is gated. This places the IC in a very low power consumption state.The register
Bit
Bit
Bit
Bit
4
5
7
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LRCK double trigger protection
Auto EAPD on clock loss
IC power-down
External amplifier power-down
RST
RST
RST
RST
1
0
1
0
Doc ID 018835 Rev 2
PWDN
EAPD
Name
Name
Name
Name
LDTE
ECLE
LRCLK double trigger protection enable
Auto EAPD on clock loss
0: IC power-down low-power condition
1: IC normal operation
0: External power stage power-down active
1: Normal operation
Description
Description
Description
Description
STA381BW