stdve103a STMicroelectronics, stdve103a Datasheet
stdve103a
Available stocks
Related parts for stdve103a
stdve103a Summary of contents
Page 1
... The device can be placed in a low-power mode by disabling the output current drivers. The differential signal from the HDMI/DVI ports can be routed through the STDVE103A to guarantee good signal quality at the HDMI receiver. Designed for very low skew, jitter and low I/O ...
Page 2
... Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 DC electrical characteristics (I2C repeater 5.4 Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5 Dynamic switching characteristics (I2C repeater Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.1 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2/44 SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STDVE103A ...
Page 3
... STDVE103A 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Contents 3/44 ...
Page 4
... Equalizer gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 21. Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 22. Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 23. Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 24. DDC I/O pins Table 25. Status pins (HPD_SINK, HPD1, HPD2, HPD3, S1, S2 Table 26. Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 27. I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 28. ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 29. TQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 30. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4/44 STDVE103A ...
Page 5
... Equalizer functional diagram (one signal pair Figure 3. DDC I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. STDVE103A in a digital TV Figure 5. Pin configuration (TQFP64 package Figure 6. STDVE103A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. TMDS output driver Figure 9. Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 10. ...
Page 6
... I/O capacitance, the switch preserves the signal integrity to pass the stringent HDMI compliance requirements. The STDVE103A provides the ability to boost the incoming TMDS signal and drive level which allows efficient signal recovery at the HDMI receiver especially useful for boosting signals for longer distance transmission when the HDMI receiver is physically distant from the HDMI input port ...
Page 7
... STDVE103A 2 Block diagram Figure 1. STDVE103A block diagram HDMI input port A HDMI input port B HDMI input port C DDC port A DDC port B DDC port C S1,S2 HPD port A HPD port B HPD port C Figure 2. Equalizer functional diagram (one signal pair) Data+ 50 Ω termination selectable Data- 3:1 HDMI ...
Page 8
... Block diagram Figure 3. DDC I A_DDC_SDA B_DDC_SDA C_DDC_SDA A_DDC_SCL B_DDC_SCL C_DDC_SCL S1, S2 2.1 Application diagrams Figure 4. STDVE103A in a digital TV 8/ bus repeater Bus Repeater Switch Game DVD-R console Digital TV STDVE103A HDMI receiver STDVE103A Y_DDC_SDA Y_DDC_SCL STB CS00063A ...
Page 9
... REXT 16 Table 2. Pin description Pin number 1-2 3 4-5 6 7-8 9 10-11 12 13-14 15 STDVE103A Pin name Type SDA3, SCL3 I/O Port3 DDC bus data and clock lines GND Power Ground B31, A31 Input, TMDS Port 3 differential inputs for channel 1 V Power Supply voltage (3.3 V ± 5%) CC B32, A32 ...
Page 10
... Input, TMDS Port 1 differential inputs for channel 3 V Power Supply voltage (3.3 V ± 5%) CC B14, A14 Input, TMDS Port 1 differential inputs for channel 4 Supply voltage (5.0 V ± 10%) for DDC, HPD and V Power DD source selector pins HPD2 Output Port 2 hot plug detector output SDA2 I/O Port 2 DDC bus data line STDVE103A Function ...
Page 11
... STDVE103A Table 2. Pin description (continued) Pin number 52 53-54 55 56-57 58 59-60 61 62-63 64 Pin name Type SCL2 I/O Port 2 DDC bus clock line B21, A21 Input, TMDS Port 2 differential inputs for channel 1 Power V Supply voltage (3.3 V ± 5%) CC B22, A22 Input, TMDS Port 2 differential inputs for channel 2 ...
Page 12
... The device conforms to the TMDS standard on both inputs and outputs. The low on-resistance and low I/O capacitance of the switch in STDVE103A result in a very small propagation delay. The device integrates SPDT-type switches for 3 differential data TMDS channels and 1 differential clock channel. Additionally, it integrates the switches for ...
Page 13
... The STDVE103A produces TMDS output levels for point-to-point links that are doubly terminated (100 the STDVE103A produces an output voltage of 3.3 – 0 2.8 V when driving a termination line terminated at each end. The input terminations are selectable thus saving power for the unselected ports. ...
Page 14
... The TMDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The device is capable of detecting differential signals as low as 100 mV within the entire common mode voltage range. 14/44 STDVE103A ...
Page 15
... STDVE103A 4.2 Operating modes 4.2.1 SEL operating modes The active source is selected by configuring source select inputs, S1 and S2. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I the selected input port is linked to the I detector (HPD) of the selected input port is output to HPD_SINK. ...
Page 16
... I C DDC bus lines to be extended without degradation in system performance. The STDVE103A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I bus, while retaining all the operating modes and features of the I two buses of 400 pF bus capacitance to be connected are operational from a supply voltage of 3 ...
Page 17
... STDVE103A 4.7 Bias The bandgap reference voltage over the external R bias reference current. This current and its factors (achieved by employing highly accurate and well matched current mirror circuit topologies) are generated on-chip and used by several internal modules. The 10 mA current used by the transmitter block is also generated using this reference current ...
Page 18
... SCL_SINK, HPD_SINK, HPD1, HPD2, HPD3, S1 output current I O Storage temperature T STG Lead temperature (10 sec Table 7. Thermal data Symbol Θ Thermal coefficient (junction-ambient) JA 18/44 Parameter Parameter STDVE103A Value -0.5 to +4.0 -0.5 to +6.0 1.7 to +4.0 -0.5 to +6.0 120 -65 to +150 300 TQFP-64 Unit TBD °C/W Unit °C ...
Page 19
... STDVE103A 5.1 Recommended operating conditions 5.2 DC electrical characteristics T = -40 to +85 ° Table 8. Power supply characteristics Symbol Parameter V Supply voltage CC V Supply voltage DD I Supply current CC I Supply current CC Supply current supply) DD Table 9. DC specifications for TMDS differential inputs Symbol Parameter Differential input high ...
Page 20
... R TERM 800 = 50 Ω R TERM 0 8 OUT± = GND through a 50 Ω resistor. See Figure 11 OUT+ or OUT- to GND when tri- state MHz STDVE103A Value Unit Typ Max V + -400 mV CC 500 600 mV 1000 1200 mV 50 µ ...
Page 21
... STDVE103A Table 11. DC specifications for SEL (S1, S2) inputs Symbol Parameter V HIGH level input voltage IH V LOW level input voltage IL V Clamp diode voltage IK I Input high current IH I Input low current IL C Input capacitance IN Table 12. Input termination resistor Symbol Parameter Differential input ...
Page 22
... MHz Switch disabled MHz Switch enabled Test condition High level guaranteed Low level guaranteed V = 3.465 5 3.465 3.3 V STDVE103A Value Unit Typ Max 5 µA 2 µ Value Unit Min Typ Max 2.0 5.3 V GND ...
Page 23
... STDVE103A HPD1, HPD2, HPD3) Table 16. Status pins ( Symbol Parameter V Voltage C Input/output capacitance I/O Output low voltage V OL (open drain I/Os) 1. Typical parameters are measured at V (1) Test condition MHz Switch disabled MHz Switch enabled +25 ° ...
Page 24
... V = 3.6 V; − O driver disabled V = 5.3 V; − O driver disabled − for the second and subsequent low levels seen ILc = 0 V. The STDVE103A should be used in applications where power is CC STDVE103A Value Unit Typ Max 3.3 3.465 V Value Unit Typ Max 5.3 V ...
Page 25
... STDVE103A 5.4 Dynamic switching characteristics T = -40 to +85 ° Typical values are at T Table 19. Clock and data rate Symbol Parameter Clock frequency f (1/10th of the CK differential data rate) D Signaling rate rate Table 20. Equalizer gain Symbol Parameter G_EQ Equalizer gain Table 21. Differential output timings ...
Page 26
... Time from OE_N to OUT± change from active to tri- state Test condition Min Refer to Section 5.5 Test condition Min pF KΩ STDVE103A Value Unit Typ Max 100 125 ps Value Unit Typ Max 12 20 ...
Page 27
... STDVE103A Table 26. Jitter Symbol Parameter (1) t Total jitter JIT 1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. Input differential voltage = V parameter is not production-tested but guaranteed through characterization on a sample-to-sample basis. ...
Page 28
... Depends on input signal rise time. Includes the 20% time intervals on both transitions. 400 KHz See Figure 19 Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20% time intervals on both transitions. STDVE103A 2 C repeater) Value Min Typ Max 100 400 4.7 1.3 4 ...
Page 29
... STDVE103A 2 (1) Table 27 repeater (continued) Symbol Parameter t High duration on SCL pin HIGH t High duration on SCL pin HIGH t Propagation delay PHL t Propagation delay PLH t Propagation delay PHL Test condition 100 KHz See Figure 19 Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. ...
Page 30
... Waveform 1 Voltage on line = 3.3 V Cmax = 400pF, Rmax = 2 K 100 KHz (2) Waveform 1 (Figure 17) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K 100 KHz (2) Waveform 1 (Figure 17) Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K STDVE103A Value Unit Min Typ Max 450 ns 250 ns 300 ns 250 ns 450 ns 300 ns 300 ...
Page 31
... STDVE103A 2 (1) Table 27 repeater (continued) Symbol Parameter t Output rise time r t Output rise time r 1. All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in production. 2. The t transition time is specified with maximum load of 2 kΩ pull-up resistance and 400 pF load capacitance. Different load r resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times ...
Page 32
... termination resistance: should be equal 32/ IN+ V IN- STDVE103A the pulse generator. OUT the cable. Both are equal STDVE103A OUT+ 100 Ω V OUT CS00065A TMDS receiver CS00069 . W ...
Page 33
... STDVE103A Figure 9. Test circuit for HDMI receiver and driver Ω TMDS TMDS receiver driver = Maximum rating 0.5pF Swing CS00071 33/44 ...
Page 34
... V 1.0 V 1.15 V 1.0 V Pulse generator Figure 11. Test circuit for short circuit output current 34/ VIN+ STDVE103A VIN- SHDN_N REXT GND 4.7 KΩ ±1% 50 Ω 50 Ω TMDS driver 50 Ω STDVE103A 10 µF 0.1 µF 0.01 µ Ω 1 Ω 3.465 V CS00072A ...
Page 35
... STDVE103A Figure 12. Propagation delays VA VCM Output Figure 13. Turn-on and turn-off times VCM V ID(p-p) V OD(O) tpLH 80% V OD(p-p) 20% tr SHDN_N 1. OFF V when V = +150mV OUT+ ID 50% V when V = -150mV OUT OFF when V = -150mV OUT+ ID when V = +150mV OUT- ID 50% Maximum rating VCC VCC – ...
Page 36
... Maximum rating Figure 14. TSK(O) Data In Data Out at Port 0 Data Out at Port 1 Figure 15. TSK(P) Figure 16. TSK(D) 36/44 tpLHX tpHLX 2.5V tpLHY tSK( tpLHy – tpLHx | or | tpHLy – tpHLx | STDVE103A 3.5V 2. tSK( 2. tpHLY ...
Page 37
... STDVE103A Figure 17. AC waveform 1 (I Figure 18. Test circuit for AC measurements (I 2 Figure 19 bus timing 2 C lines lines) Maximum rating 37/44 ...
Page 38
... Maintain 100-Ω differential transmission line impedance into and out of the STDVE103A. (b) Keep an uninterrupted ground plane below the high-speed I/Os. (c) Keep the ground-path vias to the device as close as possible to allow the shortest return current path ...
Page 39
... Master devices can be placed on either bus. Figure 20. Typical application of I Bus Master 400 kHz The STDVE103A DDC lines are 5 V tolerant does not require any extra circuitry to translate between the different bus voltages. 2 C-bus while the slave is connected bus. Both buses run at ...
Page 40
... JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ECOPACK specifications are available at: Figure 21. TQFP64 40/44 www.st.com. package outline STDVE103A ® 0.10mm .004 Seating Plane K C 0051434/E ...
Page 41
... STDVE103A Table 29. TQFP64 mechanical data Symbol Figure 22. TQFP64 tape and reel information Millimeters Min Typ 0.05 0.10 0.95 1 0.17 0.22 0.09 0.15 11.80 12 9.80 10 7.50 11.80 12 9.80 10 7.50 0.50 0.45 0.60 1 ° 0 Package mechanical data Max 1.20 0.15 1.05 0.27 0.20 12.20 10.20 12.20 10.20 0.75 ° 7 41/44 ...
Page 42
... Package mechanical data Figure 23. TQFP64 tray drawing Figure 24. TQPF64 tray drawing dimensions 42/44 STDVE103A ...
Page 43
... STDVE103A 8 Revision history Table 30. Document revision history Date 21-Jul-2008 09-Sept-2008 Revision 1 Initial release. Changed Table 1: Device summary on page 1 code. Modified the hot-plug detect status in on page 15. 2 Updated ESD information in the Features section and performance on page 31 Added TQFP64 tray drawing in page 42 ...
Page 44
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 44/44 Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STDVE103A ...