gtl2002dc NXP Semiconductors, gtl2002dc Datasheet
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GTL2002 2-bit bidirectional low voltage translator Rev. 06 — 21 December 2007 1. General description The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2002 provides 2 ...
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... GTL2002D GTL2002DP GTL2002DC GTL2002GM [1] Also known as MSOP8. 4.1 Ordering options Table 2. Type number GTL2002D GTL2002DP GTL2002DC GTL2002GM [1] ‘X’ will change based on date code. 5. Functional diagram Fig 1. Functional diagram GTL2002_6 Product data sheet 2 C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal Ordering information ...
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... DREF GREF GTL2002_6 Product data sheet 1 8 GND GREF 2 7 SREF DREF GTL2002D 002aac777 1 8 GREF DREF GTL2002DC GND 002aac779 Pin description Pin SO8, TSSOP8, VSSOP8 XQFN8U ...
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... NXP Semiconductors 7. Functional description Refer to 7.1 Function selection Table 4. Assuming the higher voltage level HIGH voltage level LOW voltage level Don’t care. [1] GREF [1] GREF should be at least 1.5 V higher than SREF for best translator operation. [ not pulled up or pulled down. ...
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... NXP Semiconductors 8. Application design-in information 8.1 Bidirectional translation For the bidirectional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF input must be connected to DREF and both pins pulled to HIGH side V DREF is recommended. The processor output can be totem pole or open-drain (pull-up ...
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... NXP Semiconductors 8.2 Unidirectional down translation For unidirectional clamping, higher voltage to lower voltage, the GREF input must be connected to DREF and both pins pulled to the higher side V (typically 200 filter capacitor on DREF is recommended. Pull-up resistors are required if the chip set I/O are open-drain. The opposite side of the reference transistor (SREF) is connected to the processor core supply voltage ...
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... NXP Semiconductors 8.4 Sizing pull-up resistor The pull-up resistor value needs to limit the current through the pass transistor when the ON state to about 15 mA. This will guarantee a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage will also be higher in the ON state ...
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... NXP Semiconductors 9. Limiting values Table 7. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V SREF V DREF V GREF REFK max T stg [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperature which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C ...
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... NXP Semiconductors 11. Static characteristics Table 9. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V LOW-level output voltage OL V input clamping voltage IK I gate input leakage current LI(gate) C input capacitance at gate ig C off-state input/output capacitance io(off) C on-state input/output capacitance ...
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... NXP Semiconductors 12. Dynamic characteristics 12.1 Dynamic characteristics for translator-type application Table 10 + amb GND = Symbol t PLH t PHL [1] All typical values are measured at V [2] Propagation delay guaranteed by characterization. Fig 9. The input (Sn) to output (Dn) propagation delays GTL2002_6 Product data sheet Dynamic characteristics for translator-type application = 1.365 V to 1.635 V ...
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... NXP Semiconductors 12.2 Dynamic characteristics for CBT-type application Table 11 + amb Symbol t PD [1] This parameter is warranted by the ON-state resistance at GREF = 4.5 V, but is not directly production tested. The propagation delay is based on the RC time constant of the typical ON-state resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance). ...
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... NXP Semiconductors 13. Test information Fig 11. Load circuit for translator-type applications Fig 12. Load circuit for CBT-type application Table 12. Test t PD GTL2002_6 Product data sheet V V DD1 DD2 200 k DREF GREF SREF V ref pulse generator from output under test Test data are given in Table 12 ...
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... NXP Semiconductors 14. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 0.15 1.55 OUTLINE VERSION IEC ...
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... NXP Semiconductors 15. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Abbreviations Table 15. Acronym CBT CDM CMOS CPU ESD GTL HBM I C-bus LVTTL MM NMOS ...
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... NXP Semiconductors 17. Revision history Table 16. Revision history Document ID Release date GTL2002_6 20071221 • Modifications: Section 2 JESD22-A115” • Section 2 from “XQFN8” to “XQFN8U” GTL2002_5 20070813 GTL2002_4 20060829 GTL2002_3 20040929 (9397 750 13058) GTL2002_2 20030401 (9397 750 11349) GTL2002_1 20000216 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Function selection Application design-in information . . . . . . . . . . 5 8.1 Bidirectional translation 8.2 Unidirectional down translation 8.3 Unidirectional up translation . . . . . . . . . . . . . . . 6 8.4 Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . . 7 9 Limiting values ...