gtl2012 NXP Semiconductors, gtl2012 Datasheet

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gtl2012

Manufacturer Part Number
gtl2012
Description
Gtl2012 2-bit Lvttl To Gtl Transceiver
Manufacturer
NXP Semiconductors
Datasheet
1. General description
2. Features
3. Quick reference data
Table 1.
Recommended operating conditions; T
[1]
Symbol
C
C
GTL; V
t
t
t
t
PLH
PHL
PLH
PHL
i
io
All typical values are measured at V
ref
= 0.8 V; V
Quick reference data
Parameter
input capacitance
input/output capacitance
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
TT
= 1.2 V
The GTL2012 is a 2-bit translating transceiver designed for 3.3 V system interface with a
GTL /GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling
receiver or as an LVTTL-to-GTL interface.
The GTL2012 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or
5 V CMOS inputs.
I
I
I
I
I
I
I
I
GTL2012
2-bit LVTTL to GTL transceiver
Rev. 01 — 9 August 2007
Operates as a 2-bit GTL /GTL/GTL+ sampling receiver or as an LVTTL to
GTL /GTL/GTL+ driver
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
GTL input and output 3.6 V tolerant
V
Partial power-down permitted
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
Package offered: TSSOP8 (MSOP8) and VSSOP8
ref
adjustable from 0.5 V to 0.5V
CC
amb
= 3.3 V and T
= 25 C
amb
Conditions
control inputs; V
A port; V
B port; V
An to Bn; see
An to Bn; see
Bn to An; see
Bn to An; see
= 25 C.
O
O
= 3.0 V or 0 V
= V
CC
Figure 4
Figure 4
Figure 5
Figure 5
TT
I
or 0 V
= 3.0 V or 0 V
Min
-
-
-
-
-
-
-
Product data sheet
Typ
2
4.6
3.4
2.8
3.4
5.2
4.9
[1]
Max
2.5
6
4.3
5
7
8
7
Unit
pF
pF
pF
ns
ns
ns
ns

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gtl2012 Summary of contents

Page 1

... The GTL2012 is a 2-bit translating transceiver designed for 3.3 V system interface with a GTL /GTL/GTL+ bus. The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling receiver LVTTL-to-GTL interface. The GTL2012 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL CMOS inputs. 2. Features I ...

Page 2

... C to +85 C amb Type number Topside mark GTL2012DP 012P GTL2012DC 012C [1] Also known as MSOP8. 5. Functional diagram Fig 1. Logic diagram of GTL2012 GTL2012_1 Product data sheet Package Name Description [1] TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm VSSOP8 plastic very thin shrink small outline package; 8 leads; ...

Page 3

... GTL2012”. Function table Input/output A (LVTTL) inputs Rev. 01 — 9 August 2007 GTL2012 2-bit LVTTL to GTL transceiver GTL2012DC DIR 3 6 GND 4 5 002aac398 Fig 3. Pin configuration for VSSOP8 B (GTL inputs © NXP B.V. 2007. All rights reserved ...

Page 4

... OFF or HIGH state; B port [2] A port B port [3] A port [1] Conditions GTL GTL GTL+ overall GTL GTL GTL+ B port except B port B port except B port B port except B port A port Rev. 01 — 9 August 2007 GTL2012 2-bit LVTTL to GTL transceiver Min 0.5 - [1] 0.5 [1] 0.5 - [1] 0.5 [1] 0 [4] 60 Min Typ Max 3 ...

Page 5

... V 0 control inputs 3 port 3 port 3.3 V and amb Rev. 01 — 9 August 2007 GTL2012 2-bit LVTTL to GTL transceiver Min Typ Max - - + +85 C. amb [1] Min Typ [2] V 0.2 - ...

Page 6

... An to Bn; see Figure An; see Figure An; see Figure amb 3 0. for B ports 3 002aab140 V = 1.5 V for B port and V for M ref A port Rev. 01 — 9 August 2007 GTL2012 2-bit LVTTL to GTL transceiver [1] Min Typ - 2.8 - 3.3 - 5.3 - 5.2 - 2.8 - 3.4 - 5.2 - 4.9 - 2.8 - 3.4 - 5 2.7 V for A ports and control pins; ...

Page 7

... Termination resistance; should be equal GTL2012_1 Product data sheet input V ref t PLH output PRR 10 MHz 2.5 ns PULSE GENERATOR PULSE GENERATOR Rev. 01 — 9 August 2007 GTL2012 2-bit LVTTL to GTL transceiver 3 ref PHL V OH 1 002aab163 2 DUT R L ...

Page 8

... 0.45 0.28 3.1 3.1 0.65 0.25 0.15 2.9 2.9 REFERENCES JEDEC JEITA Rev. 01 — 9 August 2007 2-bit LVTTL to GTL transceiver detail 5.1 0.7 0.94 0.1 0.1 0.1 4.7 0.4 EUROPEAN PROJECTION GTL2012 SOT505 (1) Z 0.70 6 0.35 0 ISSUE DATE 99-04-09 03-02-18 © NXP B.V. 2007. All rights reserved ...

Page 9

... JEDEC JEITA MO-187 Rev. 01 — 9 August 2007 2-bit LVTTL to GTL transceiver detail 3.2 0.40 0.21 0.4 0.2 0.13 0.15 0.19 3.0 EUROPEAN PROJECTION GTL2012 SOT765 ( 0.4 8 0.1 0.1 0 ISSUE DATE 02-06-07 © NXP B.V. 2007. All rights reserved ...

Page 10

... Solder bath specifications, including temperature and impurities GTL2012_1 Product data sheet Rev. 01 — 9 August 2007 GTL2012 2-bit LVTTL to GTL transceiver © NXP B.V. 2007. All rights reserved ...

Page 11

... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 10. Rev. 01 — 9 August 2007 GTL2012 2-bit LVTTL to GTL transceiver Figure 10) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...

Page 12

... Gunning Transceiver Logic Human Body Model Low Voltage Transistor-Transistor Logic Machine Model Pulse Repetition Rate Transistor-Transistor Logic Data sheet status Product data sheet Rev. 01 — 9 August 2007 GTL2012 2-bit LVTTL to GTL transceiver peak temperature 001aac844 Change notice Supersedes - - © NXP B.V. 2007. All rights reserved. ...

Page 13

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 9 August 2007 GTL2012 2-bit LVTTL to GTL transceiver © NXP B.V. 2007. All rights reserved ...

Page 14

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com GTL2012 All rights reserved. Date of release: 9 August 2007 Document identifier: GTL2012_1 ...

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